Reduced power PLA

Details Reduced power PLA Reduced power PLA

1995-04-11

1998-02-17

Westin, Edward P.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 45, H03K 19177

Patent

active

057195056

ABSTRACT:
A reduced power programmable logic array is disclosed. The circuit includes an AND array, coupled through product term lines to an output OR array. Pull-up devices in the OR array are gated to one of the active product term lines. Also disclosed is method for choosing a product term line for gating pull-up devices such that power consumption in the pull-up devices is minimized.

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IBM Technical Disclosure Bulletin, "Minimizing Power in High Performance PLA'2", vol. 32, No. 6B, Nov. 1989, pp. 362-367.
"Power Reduction Method For Static CMOS Programmable Logic Arrays (PLAS)" IBM Technical Disclosure Bulletin, V. 30, #10, pp. 247, 248, Mar. 1988.

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