Reduced power dynamic logic circuit that inhibits reevaluation o

Details Reduced power dynamic logic circuit that inhibits reevaluation o Reduced power dynamic logic circuit that inhibits reevaluation o

1998-03-27

2000-03-14

Tokar, Michael

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 93, 326 95, 326 98, 326121, H03K 1900, H03K 19096, H03K 19094

Patent

active

060378042

ABSTRACT:
A reduced-power integrated circuit includes a circuit data input, a circuit data output, and at least one row of dynamic logic. The row of dynamic logic includes a row clock input, a row data input, and a row data output coupled to the circuit data output, where a value received at the row data input is derived from the value at the circuit data input. The integrated circuit further includes a comparator that compares current and previous values at the circuit data input and a switch that selectively sets the row clock signal received at the row clock input to an inactive state and temporarily maintains the row clock signal in the inactive state in response to the comparator detecting that the current previous values of at the circuit data input are equivalent. Consequently, the row of dynamic logic does not (and need not) reevaluate the circuit data input value, and power dissipation is reduced.

REFERENCES:
patent: 5203003 (1993-04-01), Donner
patent: 5220672 (1993-06-01), Nakao et al.
patent: 5453708 (1995-09-01), Gupta et al.
patent: 5587672 (1996-12-01), Ranganathan et al.
patent: 5604454 (1997-02-01), Maguire et al.
patent: 5634131 (1997-05-01), Matter et al.
patent: 5859547 (1999-01-01), Tran et al.

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