Reduced parasitic resistance and capacitance field effect transi

Details Reduced parasitic resistance and capacitance field effect transi Reduced parasitic resistance and capacitance field effect transi

1997-12-11

1999-09-21

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257401, 257618, 438159, 438182, 438229, 438259, H01L 2972

Patent

active

059557591

ABSTRACT:
A field effect transistor and method for making the same is described wherein the field effect transistor incorporates a T-shaped gate and source and drain contacts self-aligned with preexisting shallow junction regions. The present invention provides a low resistance gate electrode and self-aligned low resistance source/drain contacts suitable for submicron FET devices, and scalable to smaller device dimensions.

REFERENCES:
patent: 5089863 (1992-02-01), Satoh et al.
patent: 5196357 (1993-03-01), Boardman et al.
patent: 5231038 (1993-07-01), Yamaguchi et al.
patent: 5268330 (1993-12-01), Givens et al.
patent: 5272100 (1993-12-01), Satoh et al.
patent: 5405787 (1995-04-01), Kurimoto
patent: 5464782 (1995-11-01), Koh
A. Acovic et al., "Novel Gate Process for 0.1 Micron MOSFETs", IBM Technical Disclosure Bulletin, vol. 36, No. 11, pp. 455-457 (Nov. 1993).

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