Reduced mask DRAM process

Details Reduced mask DRAM process Reduced mask DRAM process

1997-07-14

1998-09-15

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257762, 257763, H01L 27108

Patent

active

058083359

ABSTRACT:
A DRAM device structure, using a stacked capacitor configuration, has been developed. The stacked capacitor structure is comprised of a lower, polysilicon storage node, a thin composite dielectric layer, and an overlying capacitor plate, comprised of a composite layer of an overlying polysilicon layer, on a thin amorphous silicon layer, contacting an N type source and drain region, in a semiconductor substrate. A bit line contact structure, comprised of a metal silicide - polysilicon composite structure, is also used in the DRAM device structure. A PFET device, adjacent to the stacked capacitor DRAM device, featuring a two part contact structure, to P type source and drain regions, comprised of a wide top, aluminum - copper shape, overlying a narrower tungsten stud, is also used in this invention.

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