Reduced leakage memory cell

Details Reduced leakage memory cell Reduced leakage memory cell

2001-11-20

2003-06-03

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S063000, C365S072000

Reexamination Certificate

active

06574136

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to memory cells and more particularly relates to memory cells of reduced leakage.
Dynamic random access memory (DRAM) implementation in deep sub-micron technology, such as <0.13 micron technology, is becoming very challenging due to excessive leakage. DRAM cells incorporate a charge storage device. The voltage created by the charge represents a digital one or a digital zero depending on the value of the voltage. However, the charge leaks and must be periodically refreshed to a proper value. As the size of the cells decreases, the charge leakage becomes excessive and requires more frequent refreshing. The increased frequency of the refreshing cycle decreases memory performance. This invention addresses the problem and provides a solution.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.
BRIEF SUMMARY OF THE INVENTION
A random access memory cell made in accordance with one embodiment of the invention comprises a first conductor line, a second conductor line, a native device comprising a non-floating gate arranged to store charge and a transistor coupling the native device to the second conductor. A random access memory cell made in accordance with a second embodiment of the invention comprises a first conductor line; a second conductor line; and a native device arranged to store charge. The native device comprises a substrate body doped with n or p type material, and the substrate body defines a surface. A section of the substrate is doped with n or p type material adjacent the surface. A gate of the native device is adjacent the section, and a gating transistor couples the native device to the second conductor.
By using this memory cell, the amount of charge leakage can be reduced to a degree previously unattainable. These and other advantages and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings.


REFERENCES:
patent: 5732015 (1998-03-01), Kazerounian et al.
patent: 5793246 (1998-08-01), Vest et al.
patent: 5949710 (1999-09-01), Pass et al.
patent: 6159795 (2000-12-01), Higashitani et al.

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