Reduced glitch dynamic logic circuit and method of synthesis...

Details Reduced glitch dynamic logic circuit and method of synthesis... Reduced glitch dynamic logic circuit and method of synthesis...

2003-08-11

2008-09-30

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S112000

Reexamination Certificate

active

07429880

ABSTRACT:
The present invention implements structures and method for non-delayed clock dynamic logic circuit configurations with output and/or complementary output with reduced glitch and/or mitigating adverse charge-sharing effects for Complementary Oxide Semiconductor (CMOS) and/or mitigating parasitic bipolar action in Strained/Unstrained Silicon-On-Insulator (SOI) circuits, where insulator may be oxide, nitride of Silicon and the like or Sapphire and the like including a method of synthesis.

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R.H. Krambeck, et al. “High Speed Compact Circuits With CMOS”, IEEE JSSC SC-17(3) Jun. 1982; 614-617.

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