Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2011-03-15
2011-03-15
Ngo, Ngan (Department: 2893)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S317000, C257SE29129
Reexamination Certificate
active
07906805
ABSTRACT:
An edgeless one-transistor flash memory array includes transistors that have two polysilicon gate layers that overlay an active region. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region. An edgeless two-transistor programmable memory includes memory cells that have two active devices. Two polysilicon gate layers overlay two active regions and are shared between the two active devices. One of the devices is used to program and erase the cell while the other used as a programmable switch in a programmable logic device. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region.
REFERENCES:
patent: 5420449 (1995-05-01), Oji
patent: 5468981 (1995-11-01), Hsu
patent: 5998264 (1999-12-01), Wu
patent: 6008090 (1999-12-01), Wu
patent: 6048768 (2000-04-01), Ding et al.
patent: 6103577 (2000-08-01), Horng
patent: 6174777 (2001-01-01), Jang
patent: 6177304 (2001-01-01), Li et al.
patent: 6452835 (2002-09-01), Diorio et al.
patent: 6611032 (2003-08-01), Schuegraf et al.
patent: 6908803 (2005-06-01), Schuegraf et al.
patent: 7282759 (2007-10-01), Kim et al.
patent: 2001/0035541 (2001-11-01), Schuegraf et al.
patent: 2002/0055217 (2002-05-01), Kanamori
patent: 2008/0142870 (2008-06-01), Watanabe
patent: 2009/0039408 (2009-02-01), Hatano et al.
patent: 2009/0267130 (2009-10-01), Zhu
Byun, Young Hee et al., “An Amorphous Silicon TFT with Annular-Shaped Channel and Reduced Gate-Source Capacitance,” IEEE Transactions on Electron Devices, May 1996, vol. 43, No. 5, pp. 839-841.
Champion, Corbin L et al., “Accurate SPICE Models for CMOS Analog Radiation-Hardness-by-Design,” IEEE Transactions on Nuclear Science, Dec. 2005, vol. 52, No. 6, pp. 2542-2549.
Chen, Shiao-Shien et al., “A Comparison of Floating-Body Potential in H-Gate Ultrathin Gate Oxide Partially Depleted SOI pMOS and nMOS Devices Based on 90-nm SOI CMOS Process,” IEEE Electron Device Letters, Apr. 2004, vol. 25, No. 4, pp. 214-216.
Li, Ying et al., “Anomalous Radiation Effects in Fully Depleted SOI MOSFETs Fabricated on SIMOX,” IEEE Transactions on Nuclear Science, Dec. 2001, vol. 48, No. 6, pp. 2146-2151.
Snoeys, Walter et al., “A New NMOS Layout Structure for Radiation Tolerance,” IEEE Transaction on Nuclear Science, Aug. 2002, vol. 49, No. 4, pp. 1829-1833.
Snoeys W. et al., “Layout Techniques to Enhance the Radiation tolerance of Standard CMOS Technologies Demonstrated on a Pixel Detector Readout Chip,” Nuclear Instruments and Methods in Physics Research A 439, 2000, pp. 349-360.
Van den Bosch, Anne et al., “A High-Density, Matched Hexagonal Transistor Structure in Standard CMOS Technology for High-Speed Applications,” IEEE Transactions on Semiconductor Manufacturing, May 2000, vol. 13, No. 2, pp. 167-172.
Chan Richard
Dhaoui Fethi
McCollum John
Sadd Michael
Actel Corporation
Lewis and Roca LLP
Ngo Ngan
LandOfFree
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