Reduced duty cycle distortion using controlled body device

Details Reduced duty cycle distortion using controlled body device Reduced duty cycle distortion using controlled body device

2009-08-31

2010-11-02

Le, Don P (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S027000, C326S081000

Reexamination Certificate

active

07825693

ABSTRACT:
A semiconductor chip comprising a reference circuit and a target circuit. The reference circuit comprises a first P-channel field effect transistor (PFET) and a first N-channel field effect transistor (NFET). A reference voltage is connected to gates of the first PFET and first NFET. A body control voltage node is formed by connecting a drain of the first PFET, a body of the first PFET, a drain of the first NFET and a body of the first NFET. A target circuit comprises a second PFET and a second NFET. The body control voltage node is connected to a body of the second PFET and the second NFET. The body control voltage improves duty cycle in the target circuit compared to a similarly designed circuit having PFET bodies connected to Vdd and NFET bodies connected to Ground.

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S. C. Terry et. al. : “Adaptive Gate Biasing—A New Solution for Body-Driven Current Mirrors”, GLSVLSI'05, Apr. 17-19, 2005, Chicago, Illinois, USA, pp. 472-477.

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