Reduced device count level shifter with power savings

Details Reduced device count level shifter with power savings Reduced device count level shifter with power savings

2006-08-15

2006-08-15

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Interface

Logic level shifting

C326S083000

Reexamination Certificate

active

07091746

ABSTRACT:
A level shifting circuit includes an input node, an output node, a first power supply node, a second power supply node, a third power supply node, an inverter coupled to the first and second power supply nodes having an input coupled to the input node and an output, a transistor having a current path coupled between the output of the inverter an the output node, a first transistor circuit coupled between the first power supply node and the third power supply node having a first input coupled to the output of the inverter, a second input coupled to the output node, and an output, and a second transistor circuit coupled between the output node and the third power supply node having a first input coupled to the output of the first transistor circuit and a second input coupled to the input node.

REFERENCES:
patent: 5777497 (1998-07-01), Han
patent: 5896043 (1999-04-01), Kumagai
patent: 5917348 (1999-06-01), Chow
patent: 6531900 (2003-03-01), Hardee
patent: 6717452 (2004-04-01), Carpenter et al.
patent: 6777981 (2004-08-01), Kobayashi

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