Reduced delay power fail-safe circuit

Details Reduced delay power fail-safe circuit Reduced delay power fail-safe circuit

2005-11-15

2005-11-15

Le, Don (Department: 2819)

Electronic digital logic circuitry

Reliability

Fail-safe

C327S143000

Reexamination Certificate

active

06965250

ABSTRACT:
An improved power fail-safe has an effective maximum delay of two gate delays from an input operably powered by a first power supply to a first and a second output operably powered by a second power supply. The first and second outputs have predetermined values during an interval when the first power supply has failed and the second power supply is active. The first and second power supplies may be based at least in part on different power domains. The first power supply may be based at least in part on a core power domain and the second power supply may be based at least in part on an I/O power domain.

REFERENCES:
patent: 4649292 (1987-03-01), Rusznyak
patent: 5345422 (1994-09-01), Redwine
patent: 6472912 (2002-10-01), Chiu et al.
patent: 6737885 (2004-05-01), Shumarayev et al.
patent: 6784718 (2004-08-01), Okamoto et al.
patent: 6853221 (2005-02-01), Wert
patent: 2002/0171461 (2002-11-01), Yamazaki et al.

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