Reduced-delay clocked logic

Details Reduced-delay clocked logic Reduced-delay clocked logic

2007-03-28

2010-12-07

Du, Thuan N (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Multiple or variable intervals or frequencies

C713S600000, C326S093000

Reexamination Certificate

active

07849349

ABSTRACT:
Delay in a clocked logic circuit is reduced by partially determining a next state of the clocked logic circuit based on a current state of the clocked logic circuit during a first portion of a clock cycle. The partially determined next state of the clocked logic circuit is prevented from affecting the current state of the clocked logic circuit during the first portion of the clock cycle. The next state of the clocked logic circuit is completely determined based on a previous state of the clocked logic circuit and the partially determined next state of the clocked logic circuit during a second portion of the clock cycle.

REFERENCES:
patent: 4241418 (1980-12-01), Stanley
patent: 5250858 (1993-10-01), Strong
patent: 5598112 (1997-01-01), Phillips
patent: 7292672 (2007-11-01), Isono
Forbes, Michael et al. “Finite State Engines.” Course Paper for EE 7063 Computer Engineering, Department of Electrical Engineering, University of Tulsa, (available at http://www.personal.utulsa.edu/˜jhl/fse.pdf).

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