Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2001-02-12
2004-10-26
Auve, Glenn A. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S100000
Reexamination Certificate
active
06810459
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to computer systems, and more particularly, to the architecture of computer systems containing a central processing unit.
BACKGROUND OF THE INVENTION
Computer systems containing a central processing unit (CPU) are well known in the art. These systems may be found in many common devices such as, but not limited to, calculators, personal organizers, pagers, toys, smart cards, cellular phones, home and office appliances, consumer electronic devices, and the like. An example of one such computer system
400
is shown in FIG.
1
. The computer system
400
comprises a CPU
200
, one or more peripherals
290
,
300
,
370
,
390
, and a universal bus
100
. The CPU
200
contains circuitry for reading data and program instruction codes, decoding the instructions, and performing operations on the data according to the instructions. These operations may include steps such as, for example, moving data between peripherals and/or memory, performing mathematical operations, or making logical decisions based on the data. The peripherals
290
,
300
,
370
,
390
may include devices such as modems, memory controllers, encryption engines, timers, input/output device controllers, and the like. Although four peripherals and one CPU are shown in the example of
FIG. 1
, it will be appreciated by those of ordinary skill that any number of CPUs and peripherals may be present in such computer systems. As is known, the CPU and peripherals of the computer system
400
may be organized into bus slaves and bus masters. A bus master is a device that takes control of the universal bus
100
to read data from or write data to the bus. A bus slave is a device that does not control the flow of information on the universal bus
100
. Instead, it sends or receives data on the bus only in response to a request from a bus master. In accordance with the embodiment of
FIG. 1
, and by way of example, the CPU
200
and the peripheral
290
are bus masters, the peripherals
300
,
370
,
390
are bus slaves.
As is well understood, the universal bus
100
is a set of component buses that are used to transfer data between bus masters
200
,
290
and bus slaves
300
,
370
,
390
. The component buses comprise a universal control bus
102
, a universal feedback bus
101
, a universal address bus
103
, and a universal data bus
104
. The universal bus
100
can include any multiplexing, 3-stating, or decoding logic necessary to route the signals between the plurality of bus masters
200
,
290
and the plurality of bus slaves
300
,
370
,
390
.
The universal control bus
102
is used by the bus masters
200
,
290
to communicate read and write signals to bus slaves
300
,
370
,
390
. A read signal consists of data flowing from a bus slave
300
,
370
,
390
to a bus master
200
,
290
. A write signal consists of data flowing from a bus master to a bus slave. The universal control bus
102
is also used by the bus masters
200
,
290
to request control of the bus, since only one bus master can be in control of the bus at any time. When multiple bus masters request control of the universal bus at the same time, a peripheral frequently referred to as a universal bus arbiter
390
, mediates the various requests for control and selects a device via well known and equivalent arbitration schemes.
The universal feedback bus
101
is used by the bus slaves
300
,
370
,
390
to inform the bus masters
200
,
290
that a read or write operation has been completed. The universal feedback bus
101
is also used by the universal bus arbiter
390
to grant control of the universal bus
100
to a particular requesting bus master.
The universal address bus
103
is used by the bus masters
200
,
290
to select a particular register of a bus slave
300
,
370
,
390
or word in a memory module for read and write operations. The set of locations that can be addressed by the universal address bus
103
is called the address space of the computer system. Each location in the address space is assigned a numerical address. The locations within the address space are selected by applying the numerical addresses to physical address lines of the universal bus
103
. The relationship between the addresses that refer to the locations in the address space and the blocks of memory associated with each peripheral in the address space is called the system memory map.
FIG. 2
shows a memory map
960
for the computer system
400
of FIG.
1
. As seen from the memory map
960
, an address space
950
for the computer system
400
comprises a block of memory addresses (
951
,
953
,
955
) for peripherals
300
,
370
, and
390
respectively. Also shown in
FIG. 2
are examples of addresses that are applied to the universal address bus
103
physical address lines to select locations within the address space. Each of the universal bus
100
addresses can be split into two sections; one section selects the block of the memory map
960
for a particular peripheral, for example, the address section
961
selects the block
951
for peripheral
300
; the other section selects a particular register inside the selected memory block, for example the address section
962
selects the register
952
in the block
951
.
Referring back to
FIG. 1
, the universal data bus
104
is used by a bus master
200
,
290
when it writes data to a bus slave
300
,
370
,
390
, and is used by a bus slave
300
,
370
,
390
when a bus master
200
,
290
reads data from the bus slave
300
,
370
,
390
. In some computer systems, the universal data bus is a bi-directional bus that is used for both reading and writing data. In other computer systems the universal data bus
104
can be partitioned into two buses, a universal read data bus that propagates read data from the bus slaves
300
,
370
,
390
to the bus masters
200
,
290
and a universal write data bus that propagates the write data from the bus masters
200
,
290
to the bus slaves
300
,
370
,
390
.
The central processing unit (CPU)
200
comprises a group of registers and operation units integrated together in a unitary instruction set architecture. The instruction set architecture is characterized by a set of instruction codes and the sequences of control signals generated by decoding the instruction codes, that operate on the registers and operation units in the central processing unit
200
to execute those instruction codes. In general, the CPU
200
sequentially processes a series of instruction codes that are read over the universal bus
100
from a peripheral. The processing of each instruction code causes the CPU
200
to perform actions on data contained in the registers or interact with the peripherals over the universal bus
100
.
The group of registers of the CPU
200
comprises an instruction register
211
, a bank of data registers
220
, a bank of address registers
230
, a status register
218
, and a state register
219
. The bank of data registers primarily comprises general purpose data registers
212
,
213
that are used to hold data the CPU
200
is performing operations on. The bank of address registers comprises general purpose address registers
214
,
215
and program address registers such as a program counter
216
and stack pointer
217
.
The CPU
200
further comprises a control unit
250
, and a set of operation units
240
. The control unit
250
includes a set of control sequences
251
-
259
. Each control sequence generates the control signals necessary to fetch, decode, and execute a particular instruction code. The operation units
241
-
249
are functions that combine data and address registers in some arithmetic or logical operation specified by the instruction codes.
The registers, control unit
250
, and set of operation units
240
are connected by a number of buses that carry signals within the CPU
200
. These buses comprise an instruction bus
201
, a next state bus
206
, a current state bus
207
, a new status bus
203
, a status bus
205
, an internal control bus
202
, and an internal data
Collins Timothy J.
Crowley Michael J.
Griffin Dwight D.
Rakers Patrick L.
Auve Glenn A.
Davis Valerie M.
Hillman Val Jean F.
Motorola Inc.
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