Reduced circuit, high performance, binary select encoder network

Details Reduced circuit, high performance, binary select encoder network Reduced circuit, high performance, binary select encoder network

1994-08-12

1997-04-29

An, Meng-Ai T.

Coded data generation or conversion

Digital code to digital code converters

Tree structure

341 52, 341 92, 341160, G06F 1500

Patent

active

056258305

ABSTRACT:
This disclosure sets forth the use of input 2-bit encoders to form an encoder network capable of handling any number of encoder inputs by using the VALID output of each input 2-bit encoder as a data input to a later stage encoder and to select 2-way selector circuits using the code outputs of the input 2-bit encoders for selection of highest match.
This is accomplished through the use of first and second input 2.sup.n encoders, the first being provided with the 2.sup.n high order inputs and the second being supplied with the 2.sup.n low order inputs and the outputs of the input encoders being coupled to a single 2-input encoder and n 2-way selectors to provide an encoder network with fewer circuits and better performance due to fewer stages of delay.
If the number of desired inputs to the network is less than 2.sup.n but greater than 2.sup.n-1, known logic reduction techniques may be applied to the next higher 2.sup.n input encoder network to implement the desired 2.sup.n-1 encoder network.

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