Reduced channel length lightly doped drain transistor using...

Details Reduced channel length lightly doped drain transistor using... Reduced channel length lightly doped drain transistor using...

1999-09-20

2003-07-15

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S408000

Reexamination Certificate

active

06593623

ABSTRACT:

FIELD OF THE INVENTION
This is a continuation of application Ser. No. 09/050,730, filed Mar. 30. 1998, now U.S. Pat. No. 5,970,353.
The present invention is generally directed toward integrated circuit manufacturing and is more particularly related to a method of forming a reduced channel length lightly doped drain (RCL-LDD) transistor structure to thereby provide for a reduction in the effective channel length of the transistor without adversely increasing the vertical junction depth of the LDD extension region.
BACKGROUND OF THE INTENTION
Transistor devices make up one of the integral components of today's integrated circuits. Consequently, a reduction in the size of transistors (often called “scaling”) is constantly being pursued. Prior art
FIG. 1
is a fragmentary cross section diagram illustrating a conventional MOS type transistor
10
. The transistor
10
consists of a conductive gate region
12
overlying a thin gate oxide
14
which overlies a substrate
16
. The gate
12
and the gate oxide
14
are disposed between a drain region
18
and a source region
20
which are formed in the substrate
16
having a channel region
22
located therebetween which underlies the gate
12
and the gate oxide
14
.
As the conventional transistor
10
is scaled into the sub-micron range to reduce its dimensions and thereby improve the transistor packing density on a chip, the transistor
10
begins to experience hot-carrier effects, as illustrated in prior art FIG.
2
. These undesirable hot-carrier effects become more evident when the transistor
10
is scaled while maintaining the supply voltage constant or when the supply voltage is not reduced as rapidly as the structural features of the transistor.
The hot-carrier effects are due to an increase in the electrical field within the channel region
22
. The increased electric field causes electrons in an inversion layer
26
to be accelerated (or “heated”) to an extent that several different undesirable phenomena occur. As illustrated in prior art
FIG. 2
, the hot-carrier effects can include charge injection, substrate current and electron injection into the gate oxide
14
. Perhaps the most crucial hot-carrier effect is the charge injection into the gate oxide
14
which damages the thin oxide and leads to a time-dependent degradation of various transistor characteristics such as the threshold voltage (V
T
), the linear transconductance (g
m
) and the saturation current (I
DSAT
).
One prior art solution which reduces the undesired hot-carrier effects of traditional transistor structures is the lightly doped drain (LDD) transistor
30
, which is illustrated in prior art FIG.
3
. The LDD transistor
30
includes the gate
12
and the gate oxide
14
formed in a conventional manner, wherein a lightly doped drain extension region
32
is formed adjacent to the drain region
18
between the drain region
18
and the channel
22
. The lightly doped drain extension region
32
typically reduces the electric field near the channel region
22
by about 30-40 percent and thus the hot-carrier reliability of the transistor is greatly improved. The extension region
32
reduces the electric field by effectively dropping a portion of the drain voltage across the extension region
32
.
As transistor designers continue to scale down the transistor device dimensions, the junction depths of the source and drain regions (as well as the lightly doped drain extension region) also need to be reduced (i.e., make the junctions more shallow). Junction depths must be reduced in conjunction with scaling in order to prevent short channel transistor effects such as punchthrough and threshold voltage shift. One conventional approach to reducing the junction depth is to reduce the implant energy used to form the junctions and reduce the diffusion of the junctions in the vertical direction. Reducing the effective channel length (to get higher drive current) using the conventional approach by enhanced lateral diffusion would be accompanied by deeper junctions leading to degradation of short channel effects. Thus, using the conventional approach for a fixed gate size, the channel length cannot be reduced using the prior art method since it would result in deeper junctions. A smaller channel length would, however, be a benefit as it would help to improve the drive current. Consequently, designers have been faced with the design trade-off of reducing junction depths (to reduce short channel effects) and having longer channel lengths (leading to reduced drive current) as the transistor size is reduced.
It is an object of the present invention to overcome the limitation of the prior art by providing a decrease in the effective channel length to thereby provide for a reduced transistor sizing without experiencing transistor degradation due to short channel effects associated with deeper junctions. In other words, it is an object of the present invention to overcome the limitation posed by the conventional design methods whereby the channel length for a given gate size cannot be reduced by providing deeper junctions, as that would lead to degradation of transistor performance.
SUMMARY OF THE INVENTION
The present invention relates to a method of reducing the effective channel length of a lightly doped drain transistor without substantially impacting the junction depth of the source/drain and source/drain extension regions. Consequently, the invention allows for a reduction in transistor size without increasing the junction depth and thereby avoids the undesirable short channel effects associated with increased junction depths.
According to one aspect of the present invention a reduction in the effective channel length of a transistor without an increase in the junction depth is accomplished by performing a large tilt angle implant in conjunction with the formation of the source/drain and source/drain extension regions. The large tilt angle implant is a shallow implant and places interstitials near the lateral edge of the source/drain extension region under the gate oxide. The interstitials enhance the lateral diffusion of the source/drain extension region without substantially affecting the vertical diffusion of the source/drain and source/drain extension region. Consequently, the effective channel length of the transistor is reduced without an appreciable increase in transistor junction depth.
According to another aspect of the present invention, a first sidewall spacer is formed on the gate and the gate oxide prior to the large tilt angle implant. The first sidewall spacer has a thickness that adjusts the lateral extent to which the interstitials are formed below the gate oxide. When the first sidewall spacer is thin, the interstitials significantly extend under the gate oxide; when the sidewall spacer thickness is increased, the lateral extent to which the interstitials extend under the gate oxide is decreased. Consequently, the amount of the transistor gate-to-drain overlap capacitance can be customized independently of the junction depth of the drain and the drain extension region.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.


REFERENCES:
patent: 4755775 (1988-07-01), Marczewski et al.
patent: 4861729 (1989-08-01), Fuse et al.
patent: 5091763 (1992-02-01), Sanchez
patent: 5308780 (1994-05-01), Chou et al.
patent: 5360749 (1994-11-01), Anjum et al.
patent: 5362982 (1994-11-01), Hirase et al.
patent: 5470794 (1995-11-01), Anjum et al.
patent: 5500379 (1996-03-01), Odake et al.
patent: 5574685 (1996-1

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