Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Reexamination Certificate
2000-05-23
2001-10-09
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
C365S207000, C365S208000
Reexamination Certificate
active
06301178
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit memory devices comprising arrays of data storage cells. More specifically, the present invention relates to a method and apparatus for reducing the cell voltage required for a logical “1” to be detected.
2. Description of the Related Art
Modern electronic systems typically include a data storage device such as a dynamic random access memory (DRAM), static random access memory (SRAM) or other conventional memory devices. The memory device stores data in large arrays of memory cells. Each cell conventionally stores a single bit of data (a logical “1” or a logical “0”) and can be individually accessed or addressed. A data bit is output from a memory cell during a read operation and a data bit is stored into a memory cell during a write operation.
In a standard read or write operation, a column decoder and a row decoder translate address signals into a single intersection of a row (wordline) and column (digit line) within the memory array. This function permits a data bit to be read from the memory cell at that location or for data bit to be placed in the cell. The processing of data is dependent on the time it takes to store or retrieve individual bits of data in the memory cells. Storing and retrieving the bits of data are controlled generally by a microprocessor, whereby data are passed to and from the memory array through a fixed number of input/output (I/O) lines and I/O pins. The accuracy of sensing data is further dependent on the magnitude of charge stored in a memory cell and the capacitance inherent in the integrated circuit. Typically, a logical “1” is stored in a memory cell as V
cc
on a storage node side of a capacitor with a potential of V
cc
/2 on the common plate of the memory cell capacitor. When reading a logical “1” from the capacitor, the row line turns on the access transistor between the storage node side of the capacitor and the digit line. The charge from the storage node dumps onto the digit line and brings the voltage of the digit line up slightly above the equilibrium level of V
cc
/2 or approximately V
cc
/2 plus 50 mV. The reason that the cell only brings the digit up slightly is because of the large capacitance of the digit line with respect to the cell capacitance. Thus, the same charge that raises the storage node of the cell to V
cc
can only move the digit lines slightly above their equilibrium level of V
cc
/2.
The same principles apply to dumping a “0” onto a digit line. Even though the storage node side of the cell is at ground when the row line turns on the access gate to the cell, very little charge transferred from the digit line is needed to cause the digit line and the cell to be at the same level. This new level is slightly lower than the equilibrium level of V
cc
/2 of the digit line, or approximately V
cc
/2 minus 50 mV.
A sense amplifier uses the difference between the digit line having the memory cell dump and a reference digit line that remains at the equilibrium level to determine which line to pull up to V
cc
and which line to pull down to ground. The accuracy of the sensing operation is thus dependent on the signal clarity between sensing V
cc
/2 plus 50 mV and V
cc
/2 minus 50 mV.
Because a logical “1” in a DRAM is stored as V
cc
on the cell, the use of a high voltage (VCCP) on the gate of the access transistor and on the gate of the isolation transistor is required. This high voltage may pose reliability problems as the gate oxide thickness continues to decrease. Also, a p-channel sense amplifier is needed to pull the V
cc
/2 biased digit line up to V
cc
during a read to restore the charge in the cell. Static refresh is limited because the cell nitride has to be thick enough to withstand voltages of V
cc
/2 across it, and the reverse junction leakage and sub-threshold leakage currents of the access transistor are increased by the use of V
cc
in the cell.
SUMMARY OF THE INVENTION
The present invention involves storing a logical “1” in a memory cell at a reduced voltage of V
cc
/2 with a cell-plate voltage of V
cc
/4. Two complementary digit lines are initially biased to V
cc
/2. Because the digit lines are biased to V
cc
/2 and a logical “1” is stored as V
cc
/2, no voltage delta appears on the digit line when the access transistor is turned on. Therefore, a sense amplifier is biased to favor a logical “1” if there is no voltage differential between the digit lines in order for the data sense amplifier to correctly interpret having no voltage delta as a logical “1”. The row address is used to determine which digit line has the cell charge and which digit line is the reference. Using this approach, the gate voltages of the access device and of the isolation device do not have to be higher than V
cc
. The use of lower cell voltage produces immediate gains in static refresh times due to the reduced leakage currents.
One aspect of the present invention is a circuit using a reduced cell voltage. The circuit comprises a cell which stores a charge at a first voltage, the charge representing either a logical “1” or a logical “0”. A first digit line is initially biased to a second voltage, with the first digit line being coupled to the cell. The first voltage is substantially equal to the second voltage when a logical “1” is stored in the cell. A second digit line is biased to a third voltage. A logic detector transfers the charge on the cell to the first digit line. The charge on the cell decreases the second voltage when a logical “0” is stored in the cell and does not substantially change the second voltage when a logical “1” is stored in the cell. A sense amplifier is in electrical communication with the first digit line and the second digit line. The sense amplifier compares the second voltage to the third voltage to determine the charge stored in the cell.
Another aspect of the present invention is a method of using a reduced cell voltage in a memory cell. The method comprises the steps of storing a logic level in the memory cell at a first voltage for a logical “1” and at a second voltage for a logical “0”. A first digit line and a second digit line are biased to a reference voltage, with the first voltage being substantially equal to the reference voltage. The logic level in the memory cell is then transferred to the first digit line, and the voltage change of the first digit line is sensed. A logical “1” is output when there is substantially no voltage change on the first digit line, or a logical “0” is output when the voltage on the first digit line decreases. The method may also advantageously comprise the steps of detecting an equalization pulse and then returning the first digit line and the second digit line to the reference voltage.
Another aspect of the present invention is a memory device using a reduced voltage level in a memory cell to represent a logical “1”. The memory device comprises a pair of complementary digit lines initially biased to a first voltage level. One of the pair of complementary digit lines is a reference digit line, and one of the pair of complementary digit lines is an active digit line. A memory access circuit transfers a charge stored in the memory cell to the active digit line of the pair of complementary digit lines. A sense amplifier detects the voltage level of the pair of complementary digit lines. The sense amplifier maintains the voltage level of a first of the pair of complementary digit lines at the first voltage level and decreases the voltage level of a second of the pair of complementary digit lines to a second voltage level. A logical “0” is output when the first of the pair of complementary digit lines is the reference digit line and a logical “1” is output when the second of a pair of complementary digit lines is the reference digit line.
Another aspect of the present invention is a circuit using a reduced cell voltage. The circuit comprises a cell which stores a charge at a first voltage, the charge representing either a logical “1” or a logical “0
Derner Scott J.
Mullarkey Patrick J.
Knobbe Martens Olson & Bear LLP
Micro)n Technology, Inc.
Phan Trong
LandOfFree
Reduced cell voltage for memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Reduced cell voltage for memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reduced cell voltage for memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2595686