Reduced cell voltage for memory device

Details Reduced cell voltage for memory device Reduced cell voltage for memory device

1999-08-30

2000-08-29

Phan, Trong

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

365207, 365208, G11C 700

Patent

active

061118036

ABSTRACT:
A memory cell stores a logical "1" at a reduced voltage of V.sub.CC /2 with a cell-plate voltage of V.sub.CC /4. A pair of complementary digit lines are initially biased to V.sub.CC /2. Because the digit lines are biased to V.sub.CC /2 and a "1" is stored as V.sub.CC /2, no voltage delta appears on the digit line when the access transistor is turned on. A sense amplifier is biased to favor a logical "1" if there is no voltage differential between the digit lines in order for the data sense amplifier to correctly interpret having no voltage delta as a logical "1". The row address is used to determine which digit line has the cell charge and which digit line is the reference. Using this approach, the gate voltages of the access device and of the isolation device do not have to be higher than V.sub.CC. The use of lower cell voltage produces immediate gains in static refresh times due to the reduced leakage currents.

REFERENCES:
patent: 5726931 (1998-03-01), Zagar et al.
patent: 5732033 (1998-03-01), Mullarkey et al.
Mikio Asakura, et al.,A 34ns 256Mb DRAM with Boosted Sense-Ground Scheme, 1994 IEEE International Solid State Circuits Conference (ISSCC94), Paper TA 8.2, Feb. 17, 1994 (3 pages).
Masaki Tsukude, et al., Automatic Voltage-swing Reduction (AVR) Scheme for Ultra Low Power DRAMs, 1994 Symposium on VLSI Circuits Digest of Technical Papers, Apr. 1994, pp. 87-88.

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