Reduced capacitance lead frame for lead on chip package

Details Reduced capacitance lead frame for lead on chip package Reduced capacitance lead frame for lead on chip package

1994-11-01

1996-05-28

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

257676, H01L 23495

Patent

active

055214266

ABSTRACT:
In a lead on chip, LOC, integrated circuit packaging arrangement, the conductors terminate in fingers that receive the bond wires. Adjacent the fingers, the conductors have arm parts extending over the major face of the integrated circuit. These arm parts are formed by stamping, rolling or otherwise to present an upwardly opening channel with at least the bottom lateral margins of the arm part raised above the plane of the bottom surface of the arm part. This reduces sagging of the arm part and capacitive interaction with the integrated circuit.

REFERENCES:
patent: 4987474 (1991-01-01), Yasuhara et al.
patent: 5198883 (1993-03-01), Takahashi et al.

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