Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Reexamination Certificate
2000-06-26
2001-09-04
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
C365S207000
Reexamination Certificate
active
06285612
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a new sensing scheme for CMOS DRAM's and more particularly, to a method and associated circuit for rapidly applying an equalization voltage Vbleq other than equal to ½ Vblh
BACKGROUND OF THE INVENTION
Dynamic RAMs have been a major driving force behind VLSI technology development and their density and performance in terms of speed have increased at a very fast pace.
A most critical aspect of DRAM design is choosing a sensing scheme which can detect a small amount of charge transferred from a storage capacitor (cell) and then restore the charge back again. A typical DRAM sensing scheme involves pre-charging a bit line to a certain voltage, transferring a charge from a storage capacitor to the bit line to develop a signal on the bit line, sensing and amplifying this signal, and then restoring the charge to the storage capacitor.
As is well known in the art, the signal developed on the bit lines is highly dependent among other things, on the pre-charge voltage of the bit lines, and the bit line capacitances.
CMOS DRAMs, first introduced commercially in the 256K DRAM configuration were proven highly successful. By 1998 64 Megabit drams were available and 1 gigabit are now contemplated. These structures are the result of highly packed architectures in which the dimensions of the different elements become of the order of 0.20 &mgr;m or less. Such tight packing necessitates lowering the power supply voltage from the original 5 volts to 3.5 volts for the 16 megabit DRAMs, to 2.5 volts for the 256 Megabit DRAMs and may reach low level of 1.5 volts for a 1 Gigabit structure.
In the past, typical pre-charge levels were ½ Vblh (high voltage applied to the bit line) as this tends to be a natural voltage for the bit-lines that is easy to obtain by an equalization circuit on the bit lines. However, as the power supply voltage is reduced and the bit-line high voltage becomes lower and lower, this also results in lowering the pre-charge level of the bit-lines to the point where the overdrive on the transfer gate during signal development becomes quite small, resulting in a long signal development time. Various pre-charging techniques for sensing circuits have been developed in an effort to compensate for this problem, among the most successful being techniques that pre-charge the bit lines to ⅔ of Vblh or more in cases of PMOS arrays, and to ⅓ or less in cases of NMOS arrays.
U.S. Pat. No. 5,416,371 shows one method that obtains the ⅔ Vblh pre-charge voltage by limiting the downward swing of the bit-lines to ⅓ Vblh. This solution requires a sophisticated and complex special driver circuit increasing the cost of production. The major problem in attempting to pre-charge the bit-lines to other than ½ Vblh is that what may be called as the natural or steady state of the circuit is with the bit lines at ½ Vblh due to the circuit symmetry that results in a charge distribution that tends to equalize the bit lines at ½ Vblh. Therefore any other equalization scheme requires a substantial power supply and time to pre-charge and maintain a voltage other than the ½ Vblh on the bit lines.
There remains, therefore a need for a scheme that will permit rapidly pre-charging the bit-lines to voltages other than the ½ Vblh without needing a substantial power supply in the equalization circuit.
SUMMARY OF THE INVENTION
To meet this and other needs, and in view of its purposes, it is an object of the present invention to provide a circuit that permits to pre-charge bit lines to a desired voltage Vbleq other than Vblh/2. Specifically, the invention is a DRAM semiconductor circuit comprising:
a) plurality of block cell arrays each array comprising a plurality of complementary pairs of bit lines, and control lines to selectively activate a desired one of the plurality of array blocks;
b) a plurality of shared sense amplifiers connected to the pairs of bit lines;
c) an equalization circuit connected between each of the bit line pairs of each of the array blocks, between each of the array blocks and the shared sense amplifiers;
d) a charge flow circuit also connected between each of the bit line pairs of each of the array blocks, between each of the array blocks and the shared sense amplifiers; and
e) a charge flow circuit control line connected to the charge flow circuits for connecting the charge flow circuit to an electrical ground, thereby to act as a discharge circuit.
In an alternate embodiment the charge flow circuit is connected instead of an electrical ground to the bit line high voltage (Vblh). In this embodiment the charge flow circuit acts as a charging circuit.
It is a further object of this invention to provide a method for obtaining a desired bit line equalization voltage in a dram circuit comprising an active and an inactive block of bit line arrays alternatively connected to shared sense amplifiers, said equalization voltage being a fraction of an applied bit line high voltage Vblh less than ½ Vblh, the method comprising calculating a number of bit line pairs to be discharged by grounding, using the following relationship:
Number of bit lines to be discharged in inactive block=[number of high bit lines in active block/desired fraction of Vblh]−Total number of bit lines in active block,
and discharging by grounding this number of bit lines in the inactive block.
It is also an object of this invention to provide a method for obtaining a desired bit line equalization voltage in a dram circuit comprising an active and an inactive block of bit line arrays alternatively connected to shared sense amplifiers, said equalization voltage being a fraction of an applied bit line high voltage Vblh greater than ½ Vblh, the method comprising calculating a number of bit line pairs to be charged by connecting to the bit line high voltage, using the following relationship:
Number of bit lines to be connected to Vblh in inactive block=[number of low bit lines in active block/(1-desired fraction of Vblh)]−Total number of bit lines in active block,
And connecting this number of bit lines in the inactive block to the bit line high voltage.
It is understood that the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
REFERENCES:
patent: 4816706 (1989-03-01), Dhong et al.
patent: 5416371 (1995-05-01), Katayama et al.
patent: 5689461 (1997-11-01), Kaneko et al.
patent: 5815451 (1998-09-01), Tsuchida
patent: 5844853 (1998-12-01), Kitsukawa et al.
patent: 5970007 (1999-10-01), Shiratake
patent: 6097652 (2000-08-01), Roh
IBM Technical Disclosure Bulletin, Vo. 36, No. 1, pp. 286-289 (Jan. 1993).
S.H. Dhong et al., “High-Speed Sensing Scheme for CMOS DRAMS's”, IEEE Journal of Solid-State Circuits, vol. 23, No. 1 pp. 34-40 (Feb. 1988).
International Business Machines - Corporation
Phan Trong
Ratner & Prestia
Townsend, Esq. Tiffany L.
LandOfFree
Reduced bit line equalization level sensing scheme does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Reduced bit line equalization level sensing scheme, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reduced bit line equalization level sensing scheme will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2513837