Reduced area storage node junction

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257304, 257305, H01L 27108, H01L 2976

Patent

active

056082495

ABSTRACT:
An improved storage node junction between a doped active area in a semiconductor substrate and an overlying layer of polysilicon, such as the storage node junction in a DRAM memory cell. The area and perimeter of the storage node junction is significantly reduced and the junction is moved away from the adjacent isolation structure. An exemplary semiconductor device incorporating the new junction includes a storage node junction between a conductive polysilicon layer and an active area on a semiconductor substrate, the substrate having been subjected to LOCOS steps to create active areas bounded by a region of field oxide. An insulated gate electrode is formed over an active area on the substrate, which has been doped to a first conductivity type. A contact region comprising a portion of the active area extends laterally between one side of the gate electrode and the field oxide region. The contact region has a first segment adjacent to the gate electrode and a second segment interposed between the first segment and the field oxide region. The first segment is thereby isolated from the field oxide region by the second segment. The first segment is doped to a second conductivity type. A layer of storage polysilicon is formed in electrical contact with the first segment of the contact region but not the second segment of the contact region. The storage polysilicon is isolated from the field oxide through an insulating layer interposed between the storage polysilicon and the second segment of the contact region.

REFERENCES:
patent: 5234856 (1993-08-01), Gonzalez
patent: 5320974 (1994-06-01), Hori et al.
patent: 5406512 (1995-04-01), Kagenishi
patent: 5422315 (1995-06-01), Kobayashi

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