Reduced area product-term array

Details Reduced area product-term array Reduced area product-term array

1998-03-24

2001-03-06

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S041000, C326S038000, C326S039000, C326S040000

Reexamination Certificate

active

06198305

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to product-term arrays generally and, more particularly, to reduced area product-term arrays.
BACKGROUND OF THE INVENTION
A complex programmable logic device (CPLD) has a number of logic blocks each containing a number of individual programmable macrocells. CPLDs can be easily programmed by engineers in the field and later erased and re-programmed. This allows the designer to make any changes to their system very late in the development cycle, thus realizing a competitive design advantage.
Product-term arrays inside a CPLD are created by providing both a positive and negative polarity of a number of signals that are presented as inputs to the product-term array.
FIG. 1
illustrates a product-term array
10
having such a configuration. The product-term array
10
generally comprises a number of inputs
12
a-
12
n
and a number of outputs
14
a-
14
n.
Each of the inputs
12
a-
12
n
is presented to one of a number of buffers
16
a-
16
n
. Each of the buffers
16
a-
16
n
presents both a true and a complement output of the signal received at the respective input
12
a-
12
n.
For example, the buffer
16
a
has a true output
18
a
and a complement output
20
a.
The outputs
18
a-
18
n
and
20
a-
20
n
are presented to a number of product-term input lines
22
a-
22
n
and
24
a-
24
n
, respectively. The product-term input lines
22
a-
22
n
and
24
a-
24
n
are extended in a vertical direction by a number of vertical lines
30
a-
30
n
. The vertical lines
30
a-
30
n
generally cross a number of product-term lines
32
a-
32
n,
which are generally presented to a number of logic gates
34
a-
34
n.
The logic gates
34
a-
34
n
generally present signals to the outputs
14
a-
14
n.
The disadvantages of providing both the positive and negative polarities (i.e., the true and complement signals) of each input signal
12
a-
12
n
include (i) an increased area needed to implement the outputs
22
a-
22
n
and
24
a-
24
n
for each of the buffers
16
a-
16
n
and (ii) longer overall propagation delays due to the increased length of the product-term lines
32
a-
32
n.
By increasing the length of the product-term lines
32
a-
32
n,
additional silicon die area is required. An increased capacitance on the product-term lines
32
a-
32
n
and the product-term input lines
22
a-
22
n
(and
24
a-
24
n
) increases the propagation delays through the product-term array
10
.
SUMMARY OF THE INVENTION
The present invention concerns a product-term array that may allow for the implementation of product terms requiring less silicon area than conventional designs. The product terms may also have a shorter propagation delay when compared with conventional designs. A multiplexer, which may be programmed with a configuration bit or signal, may select the polarity of an input signal to the product-term array. Duplicating a number of the initial inputs to the array may accommodate particular design constraints that may require both polarities (i.e., both positive and negative) of a given signal or set of signals. Even with the duplication of certain inputs, the total number of product-term inputs to the array will generally be reduced when compared with conventional designs that duplicate the polarity of every input internally to the array.
The objects, features and advantages of the present invention include providing a product-term array that (i) reduces the silicon area required for implementation, (ii) reduces the propagation delays through the product-term array, (iii) provides a similar logic capability as a conventional product-term array, and (iv) allows AND-terms to be created from signals or inputs to the array.


REFERENCES:
patent: 4447894 (1984-05-01), Imamura
patent: 4667310 (1987-05-01), Takada
patent: 4871930 (1989-10-01), Wong et al.
patent: 5216636 (1993-06-01), Runaldue
patent: 5652529 (1997-07-01), Gould et al.
patent: 5670896 (1997-09-01), Diba et al.
patent: 5691653 (1997-11-01), Mendel
patent: 5764080 (1998-06-01), Huang et al.
patent: 5966027 (1999-10-01), Kapusta et al.

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