Reduced area freeze logic for programmable logic blocks

Details Reduced area freeze logic for programmable logic blocks Reduced area freeze logic for programmable logic blocks

2007-06-26

2007-06-26

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S047000

Reexamination Certificate

active

11215597

ABSTRACT:
Techniques are provided for implementing freeze logic on programmable logic blocks. The output signal of a register in each programmable logic block is driven to a predefined state in response to a freeze signal. The freeze signal also causes a multiplexer in each programmable logic block to select the output signal of the register. The multiplexer drives an output signal of the programmable logic block to a predefined state to eliminate contention between circuit elements. The freeze logic requires a small amount of area in each programmable logic block.

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