Reduce line end pull back by exposing and etching space...

Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching

Reexamination Certificate

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Details

C438S720000

Reexamination Certificate

active

07015148

ABSTRACT:
The invention is a method of manufacturing a semiconductor device and such semiconductor device. The semiconductor device includes an integrated circuit pattern including a horizontal line, a vertical line and a space therebetween, the space including a precise width dimension. The method includes the steps of: forming a photosensitive layer to be patterned, patterning the photosensitive layer to form a pattern including a master horizontal line and a master vertical line without a space therebetween, transferring the pattern to at least one underlying layer using the patterned photosensitive layer, forming a second photosensitive layer over the patterned at least one underlying layer, patterning the second photosensitive layer to form a second pattern including a master space aligned to dissect a horizontal line and a vertical line formed in the at least one underlying layer, and transferring the second pattern to the at least one underlying layer to form a third pattern including a horizontal line and a vertical line with a space therebetween, the space including a precise width dimension.

REFERENCES:
patent: 6022815 (2000-02-01), Doyle et al.
patent: 6249904 (2001-06-01), Cobb
patent: 6335128 (2002-01-01), Cobb et al.
patent: 6391525 (2002-05-01), Lyons
patent: 6430737 (2002-08-01), Cobb et al.
patent: 6455205 (2002-09-01), Cobb et al.
patent: 6467076 (2002-10-01), Cobb
patent: 6516459 (2003-02-01), Sahouria
patent: 6643616 (2003-11-01), Granik et al.
patent: 6664173 (2003-12-01), Doyle et al.
patent: 6838347 (2005-01-01), Liu et al.
Claims from U.S. Appl. No. 10/852,876, Filing Date May 25, 2004.

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