Redriving a data signal responsive to either a sampling...

Details Redriving a data signal responsive to either a sampling... Redriving a data signal responsive to either a sampling...

2006-10-24

2006-10-24

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S300000, C713S400000, C713S500000, C375S354000, C359S199200, C326S021000

Reexamination Certificate

active

07127629

ABSTRACT:
A method and apparatus for redriving a data signal adjusts a sampling clock signal responsive to the data signal. An embodiment of an I/O cell may include a receiver to receive and redrive a data signal responsive to a sampling clock signal, and a sampling clock generator coupled to the receiver to generate the sampling clock signal, wherein the sampling clock generator is capable of adjusting the sampling clock signal responsive to the data signal.

REFERENCES:
patent: 5742840 (1998-04-01), Hansen et al.
patent: 5748872 (1998-05-01), Norman
patent: 5860080 (1999-01-01), James et al.
patent: 5867422 (1999-02-01), John
patent: 5898863 (1999-04-01), Ofer et al.
patent: 6006318 (1999-12-01), Hansen et al.
patent: 6034878 (2000-03-01), Osaka et al.
patent: 6038682 (2000-03-01), Norman
patent: 6092229 (2000-07-01), Boyle et al.
patent: 6125419 (2000-09-01), Umemura et al.
patent: 6128750 (2000-10-01), Espy et al.
patent: 6151648 (2000-11-01), Haq
patent: 6154826 (2000-11-01), Wulf et al.
patent: 6154855 (2000-11-01), Norman
patent: 6160423 (2000-12-01), Haq
patent: 6185644 (2001-02-01), Farmwald et al.
patent: 6255859 (2001-07-01), Haq
patent: 6263413 (2001-07-01), Motomura et al.
patent: 6317352 (2001-11-01), Halbert et al.
patent: 6327205 (2001-12-01), Haq
patent: 6345321 (2002-02-01), Litaize et al.
patent: 6369605 (2002-04-01), Bonella et al.
patent: 6408402 (2002-06-01), Norman
patent: 6449213 (2002-09-01), Dodd et al.
patent: 6487102 (2002-11-01), Halbert et al.
patent: 6493250 (2002-12-01), Halbert et al.
patent: 6502161 (2002-12-01), Perego et al.
patent: 6513080 (2003-01-01), Haq
patent: 6625687 (2003-09-01), Halbert et al.
patent: 6643752 (2003-11-01), Donnelly et al.
patent: PCT/US98/22324 (1999-05-01), None
patent: WO 99/30240 (1999-06-01), None
patent: WO 99/41666 (1999-08-01), None
patent: WO 99/41667 (1999-08-01), None
U.S. Appl. No. 10/713,868, filed Nov. 14, 2003, Pete D. Vogt.
U.S. Appl. No. 10/714,025, filed Nov. 14, 2003, Pete D. Vogt.
U.S. Appl. No. 10/714,026, filed Nov. 14, 2003, Pete D. Vogt.
U.S. Appl. No. 10/883,474, filed Jun. 30, 2004, Pete D. Vogt.
U.S. Appl. No. 10/882,999, filed Jun. 30, 2004, Pete D. Vogt.
U.S. Appl. No. 10/859,438, filed May 31, 2004, Pete D. Vogt.
U.S. Appl. No. 10/858,850, filed May 31, 2004, Pete D. Vogt.
U.S. Appl. No. 10/859,060, filed May 31, 2004, Pete D. Vogt.
The Institute of Electrical and Electronics Engineers, Inc.,IEEE Standard for Scalable Coherent Interface(SCI), May 23, 2001, 1-243 pp.
R. Ng (Sun Microsystems, Inc.),Fast Computer Memories,IEEE Spectrum, Oct. 1992, pp. 36-39.
R.H.W. Salters (Philips Research Laboratories),Fast DRAMs for Sharper TV,IEEE Spectrum, Oct. 1992, pp. 40-42.
F. Jones (United Memories, Inc.),A New Era of Fast Dynamic RAMs,IEEE Spectrum, Oct. 1992, pp. 43-49.
M. Farmwald and D. Mooring (Rambus, Inc.),A Fast Path to One Memory,IEEE Spectrum, Oct. 1992, pp. 50-51.
S. Gjessing (University of Oslo), D.B. Gustavson (Stanford Linear Accelerator Center), D.V. James and G. Stone (Apple Computer, Inc.) and H. Wigger (Hewlett-Packard Co.),A RAM Link for High Speed,IEEE Spectrum, Oct. 1992, pp. 52-53.
The Institute of Electrical and Electronics Engineers, Inc.,IEEE Standard for High-Bandwidth Memory Interface Based on Scalable Coherent Interface(SCI)Signaling Technology(RamLink), 1996, 1-91 pp.
U.S. Appl. No. 10/454,399, filed Jun. 3, 2003 entitled Memory Channel With Hot Add/Remove by Pete D. Vogt.
U.S. Appl. No. 10/454,400, filed Jun. 3, 2003, entitled Memory Channel Utilizing Permuting Status Patterns by Pete D. Vogt and James W. Alexander.
U.S. Appl. No. 10/456,353, filed Jun. 5, 2003, entitled Memory Channel With Bit Lane Fail-Over by Pete D. Vogt.
U.S. Appl. No. 10/456,206, filed Jun. 4, 2003, entitled Memory Channel Having Deskew Separate From Redrive by Pete D. Vogt.
U.S. Appl. No. 10/456,178, filed Jun. 4, 2003, entitled Memory Channel With Redundant Presence Detect by Pete D. Vogt.
U.S. Appl. No. 10/456,174, filed Jun. 4, 2003, entitled Memory Channel With Unidirectional Links by Pete D. Vogt.
B. Kim, D. Helman and P. Gray,A 30-MHz Hybrid Analog/Digital Clock Recovery Circuit in 2-μm CMOS,IEEE Journal of Solid-State Circuits, vol. 25, No. 6, Dec. 1990, pp. 1385-1394.
S. Kasturia, J. Winters,Techniques for High-Speed Implementation of Nonlinear Cancellation,Jun. 1991 IEEE Journal on Selected Areas in Communications, vol. 9, No. 5, pp. 711-717.
Microprocessor and Microcomputer Standards Subcommittee of the IEEE Computer Society,IEEE Standard for Scalable Coherent Interface(SCI), IEEE Std 1596-1992, Mar. 1992, cover sheet and pp. 226-229.
T. Hu and P. Gray,TA 6.2: A Monolithic 480Mb/s Parallel AGC/Decision/Clock-Recovery Circuit in 1.2 μm CMOS,ISSCC 93/Session 6/Broadband Data Communications/Paper TA 6.2, Feb. 1993, pp. 98-99 and p. 269.
M. Banu and A. Dunlop,TA 6.4: A 660Mb/s Clock Recovery Circuit with Instantaneous Locking for NRZ Data and Burst-Mode Transmission,ISSCC 93/Session 6/Broadband Data Communications/Paper TA 6.4, Feb. 1993, pp. 102-103 and p. 270.
M. Soyuer and H. Ainspan,TP 10.4: A Monolithic 2.3Gb/s 100mW Clock and Data Recovery Circuit,ISSOC 93/Session 10/High-Speed Communication and Interfaces/Paper TP 10.4, Feb. 1993, pp. 158-159 and 282.
A. Pottbacker and U. Langmann,TA 6.5: An 8-GHz Silicon Bipolar Clock-Recovery and Data-Regenerator IC,ISSCC 94/Session 6/Clock and Data Recovery/Paper TA 6.5, Feb. 1994, pp. 116-117.
C. Svensson and J. Yuan,A 3-Level Asynchronous Protocol for a Differential Two-Wire Communication Link,IEEE Journal of Solid-State Circuits, vol. 29, No. 9, Sep. 1994, pp. 1129-1132.
T. Lee, K. Donnelly, J. Ho, J. Zerbe, M. Johnson, T. Ishikawa,A 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabyte/s DRAM,Dec. 1994 IEEE Journal of Solid-State Circuits, vol. 29, No. 12.
C. Yang and M. Horowitz,A 0.8-μm CMOS 2.5 Gb/s Oversampling Receiver and Transmitter for Serial Links,IEEE Journal of Solid-State Circuits, vol. 31, No. 12, Dec. 1996, pp. 2015-2023.
S. Sidiropoulos, M. Horowitz,A Semidigital Dual Delay-Locked Loop,Nov. 1997 IEEE Journal of Solid-State Circuits, vol. 32, No. 11, pp. 1683-1692.
S. Sidiropoulos, M. Horowitz, SA 20.2:A Semi-Digital DDL with Unlimited Phase Shift Capability and 0.08-400 MHz Operating Range,Dec. 1997, 10 pages.
S. Sidiropoulos,High Performance Inter-Chip Signalling, Technical Report No. CSL-TR-98-760,Apr. 1998, Computer Systems Laboratory Departments of Electrical Engineering and Computer Science, cover sheet, pp. ii, iii, iv, iii, iv, v, vi, vii, viii, ix, x, pp. 1-127.
M. Horowitz,Lecture 15: Clock Recovery,Computer Systems Laboratory, 2001, 18 pages.
R. Prentice, S. Rogers, B. Payne,XAUI: Curing Internal Speed Blockages,Jan. 2002, EE Times, pp. 1-4 printed from eetimes.com website and Figure 1 and Figures 2 attached to end of article.
Designing Multi-Gigabit Serial Backplanes with High Speed SERDES Solutions Marketing White Paper,Nov. 2002 PMC-Sierra Article, pp. 1-15.

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