Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2006-12-19
2006-12-19
Kebede, Brook (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C257S778000, C257S738000, C438S106000, C438S119000, C438S613000
Reexamination Certificate
active
07151012
ABSTRACT:
A wafer comprises a wafer, a conductor, a first passivation layer, a second passivation layer, a redistribution layer, and a third passivation layer. The conductor is disposed on the wafer. The first passivation layer covers the wafer, and exposes the surface of the conductor. The second passivation layer having an aperture is formed on the first passivation layer, and the aperture relatively to a pre-designed line exposes the surface of the conductor. The redistribution layer comprising a first and second metallic layer is formed in the aperture. The first metallic layer is disposed in the aperture. The second metallic layer peripherally covers the first metallic layer, and is connected to the inner wall of the aperture formed by the first passivation layer, second passivation layer and the conductor. The third passivation layer is formed on the second passivation layer and the first metallic layer of the redistribution layer.
REFERENCES:
patent: 6492198 (2002-12-01), Hwang
Advanced Semiconductor Engineering Inc.
Kebede Brook
Kim Su C.
Thomas Kayden Horstemeyer & Risley
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