Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2007-05-30
2008-07-15
Le, Don P (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S098000, C326S034000
Reexamination Certificate
active
07400175
ABSTRACT:
In one embodiment, a circuit includes a first circuit block connected to ground via a first sleep transistor, a virtual ground node between the first circuit block and the first sleep transistor, a second circuit block connected to a supply via a second sleep transistor, and a virtual supply node between the second circuit block and the second sleep transistor. The circuit also includes a transmission gate (TG) or a pass transistor connecting the virtual ground node to the virtual supply node to enable charge recycling between the first circuit block and the second circuit block during transitions by the circuit between active mode and sleep mode.
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Fallah Farzan
Pakbaznia Ehsan
Pedram Massoud
Baker & Botts L.L.P.
Le Don P
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