Recyclable flip-chip semiconductor device

Details Recyclable flip-chip semiconductor device Recyclable flip-chip semiconductor device

2001-02-21

2004-05-11

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Flip chip

C257S779000, C257S783000, C257S786000

Reexamination Certificate

active

06734566

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a flip-chip type semiconductor device obtained by mounting a semiconductor chip on a multi-layered wiring substrate and a manufacturing method of the same and, more particularly, to a flip-chip type semiconductor device which can be recycled, has high mounting reliability, and can be manufactured at a low cost and a method of manufacturing the same.
2. Description of the Related Art
FIG. 1A
is an illustration showing a conventional flip-chip type semiconductor device, and
FIG. 1B
is an illustration showing a mounting state of a conventional flip-chip type semiconductor device.
As shown in
FIG. 1A
, in a conventional flip-chip type semiconductor device
100
, projecting solder bumps
101
consisting of a solder or a metal material such as Au or an Sn—Ag-based alloy are formed on external terminals which are provided in area array arrangement on a peripheral portion or an active region of a chip.
The flip-chip type semiconductor device
100
is mounted on a multi-layered wiring substrate
102
(mounting substrate) on which electrode pads (not shown) are formed in the same pattern as the bump arrangement pattern of the flip-chip type semiconductor device
100
on the side of an end user. When the flip-chip type semiconductor device
100
is mounted on the multi-layered wiring substrate
102
, if a bump material is a solder, the flip-chip type semiconductor device
100
is mounted by an IR reflow (infrared reflow) process using a flux.
However, after the conventional flip-chip type semiconductor device
100
is mounted on the multi-layered-wiring substrate
102
, due to incoincidence (mismatch) between linear expansion coefficients of the multi-layered wiring substrate
102
and the flip-chip type semiconductor device
100
, especially, the temperature cycle characteristics of the mounting reliability are degraded disadvantageously. In order to solve the problem, the following measure is conventionally performed.
In order to make the linear expansion coefficient of the multi-layered wiring substrate close to the linear expansion coefficient of silicon, a ceramic-based material such as AlN, mullite, or glass ceramics which is substantially expensive among a material is used to minimize the mismatch between the linear expansion coefficients, thereby performing an attempt to improve the mounting reliability. This attempt is effective from the viewpoint of improvement in mounting reliability. However, since the expensive ceramic-based material is used as the material of the multi-layered wiring substrate, the application of the measure is limited to a super computer, a large-scale computer, or the like which is generally maximally expensive.
In contrast to this, in recent years, the following technique is proposed. That is, an under fill resin is arranged between a semiconductor chip and a multi-layered wiring substrate which is relatively low in cost and which uses an organic material having a large linear expansion coefficient to construct a flip-chip semiconductor device, so that mounting reliability can be improved. In this manner, the under fill resin is arranged between a semiconductor chip and a multi-layered wiring substrate using an organic material, so that a shearing stress acting on a bump joint portion existing between the semiconductor chip and the multi-layered wiring substrate using the organic material is dispersed, and the mounting reliability can be improved. When the under fill resin is interposed between the semiconductor chip and the multi-layered wiring substrate using the organic material, a multi-layered wiring substrate using an inexpensive organic material can be used.
However, in this conventional technique, when a void exists in the under fill resin, or when the adhesive characteristics of an interface between the under fill resin and the semiconductor chip and an interface between the under fill resin and the multi-layered wiring substrate using an organic material are poor, in a moist absorption reflow process of a product, a peeling phenomenon occurs on the interface, and a defective product is manufactured disadvantageously. For this reason, the conventional technique cannot reliably advance a reduction in cost of a flip-flop type semiconductor device.
In addition, since a flip-chip type semiconductor chip is generally used in an LSI having high performance, the products itself is expensive. Therefore, when a portion except for the semiconductor chip is defective in an electric selection process performed after the flip-chip type semiconductor chip is mounted on a multi-layered wiring substrate, non-defective semiconductor chip must be recycled. However, when an under fill resin is interposed between the semiconductor chip and the multi-layered wiring substrate using an organic material, the semiconductor chip cannot be recycled. In this case, since peripheral devices including the multi-layered wiring substrate using the organic material become defective, a reduction in cost can hardly be always advanced by using the multi-layered wiring substrate using the organic material.
On the other hand, when a ceramic-based multi-layered wiring substrate is used in a semiconductor chip, the linear expansion coefficient of the ceramic-based material is optimized to eliminate the necessity of an under fill resin. For this reason, a recycle process for a non-defective semiconductor chip can be relatively made easy.
FIG. 2A
is an illustration showing a removing method of a flip-chip type semiconductor device, and
FIG. 2B
is an illustration showing the flip-chip type semiconductor device after the removal. When a semiconductor device
100
is to be recycled, a heating absorption tool
103
absorbs the semiconductor device
100
by sucking the semiconductor device
100
by means of a vacuum device (not shown) connected to an exhaust pipe
104
formed in the heating absorption tool
103
, and the semiconductor device
100
is heated to a high temperature by a heater
105
to melt solder bumps
101
on the rear surface of the semiconductor device
100
, thereby drawing the semiconductor device
100
from the multi-layered wiring substrate
102
. In this manner, the non-defective semiconductor device
100
can be removed.
However, when the semiconductor device
100
is removed, the semiconductor device
100
is heated to a high temperature. For this reason, a passivation film consisting of a polyimide (PI)-based organic material or an inorganic material such as SiO and formed to protect the solder bumps
101
a
of the removed semiconductor device
100
or the barrier metal joint portion between the solder bumps
101
and the semiconductor device
100
, and the active region of the semiconductor device
100
is damaged. For this reason, the non-defective semiconductor chip may be defective. In this manner, due to the above-described problem, it is difficult to recycle a non-defective flip-chip type semiconductor chip in the conventional technique.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a flip-chip type semiconductor device which can be recycled, has high mounting reliability, and can be manufactured at a low cost and a method of manufacturing the same.
A flip-chip type semiconductor device according to the present invention includes a semiconductor substrate, a pad electrode formed on the semiconductor substrate, an insulating film formed on the entire surface of the semiconductor substrate to be opened above the pad electrode, a wiring portion patterned on the pad electrode and the insulating film, an electrode formed on the wiring portion, a metal bump formed on the electrode, a support plate in which holes each having a diameter larger than the diameter of the metal bump are formed at positions adjusted to the metal bumps and which is arranged such that the metal bumps project with an appropriate interval above the semiconductor substrate, and an insulating resin layer formed to bury the electrode between the semiconductor substrate and

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