Computer graphics processing and selective visual display system – Computer graphics display memory system – Graphic display memory controller
Reexamination Certificate
2007-02-13
2007-02-13
Nguyen, Phu K. (Department: 2628)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Graphic display memory controller
C345S520000, C370S395620
Reexamination Certificate
active
11011227
ABSTRACT:
A receiver for recovering a serial clock of a transmitter is provided. The receiver comprises a buffer configured to store packets received from the transmitter. The packets may be sent through a packet switched network that may incur packet delay during transmission through the network. A memory controller is configured to determine a fill level of the buffer. A frequency generator is configured to generate a clock frequency, where the frequency is used to determine when to read packets from the buffer. A frequency controller is configured to instantaneously adjust the frequency of the frequency generator based on an algorithm that determines the clock frequency based on the fill level of the buffer. Accordingly, by adjusting the frequency outputted by the frequency generator, the frequency controller is able to recover the serial clock of the transmitter.
REFERENCES:
patent: 5699391 (1997-12-01), Mazzurco et al.
patent: 6167048 (2000-12-01), Law et al.
patent: 6999480 (2006-02-01), Subrahmanyan et al.
Network Equipment Technologies Inc.
Nguyen Phu K.
LandOfFree
Recovery of a serial bitstream clock at a receiver in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Recovery of a serial bitstream clock at a receiver in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Recovery of a serial bitstream clock at a receiver in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3877680