Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2000-08-31
2003-11-18
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
06651212
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a recording/reproduction device, semiconductor memory, and memory card using the semiconductor memory, and particularly to a recording/reproduction device which utilizes both of the error correcting ability of the semiconductor memory and the error correcting ability of the controller of the device. According to the present invention, the process can be simplified even in case the semiconductor memory of a device has a unit data size of erasure larger than the unit data size of processing by the device. The inventive recording/reproduction device is fairly reliable and is inexpensive.
2. Description of the Prior Art
A flash memory disk which is an example of recording/reproduction devices using non-volatile semiconductor memories is made up of flash memory chips, an interface chip, a microprocessor, etc. as shown in
FIG. 1
of Japanese Patent Unexamined Publication No. H9-305497.
The flash memory chip is liable to have an increased error rate when the write operation exceeds a certain number of times, and therefore it relies on the error correcting function (inclusive of the error detecting function) of the interface chip or microprocessor to retain the reliability of the flash memory disk.
The flash memory chip is also often used as a discrete part. Therefore, the flash memory chip is designed to have an error correcting function by itself so that it has a certain level of reliability, as disclosed in Japanese Patent Unexamined Publication No. H3-5995.
It is known that a variable-length format scheme for a mass magnetic disk system uses a concatenated code to reduce redundant bytes of the error correction code so as to enhance the efficiency of error correction, as disclosed in Japanese Patent Unexamined Publications No. S59-165541, No. S62-73336 and No. H1-155721.
In case flash memory chips having an error correcting function are used for a system, such as a flash memory disk, which is required to be more reliable than the flash memory chips as discrete parts, it is necessary to include a controller having a high-grade error correcting function outside the flash memory chips. It is problematic however in that the use of the error correcting function of the flash memory chip make a miss-correction, resulting in a degraded reliability of the system as the whole, and therefore this error correcting function is not always useful.
For example, when flash memory chips having an error correcting function for dealing with 1-byte errors are used for a system which necessitates the correction of up to 3-byte errors, a controller capable of correcting 3-byte errors is included in the system. A 3-byte error arising in a flash memory chip can be corrected by the controller without using the error correcting function of the flash memory chips. If, on the other hand, correction of the error by the error correcting function of the flash memory chip is attempted, it occasionally make a miss-correction due to the error beyond its ability and convert the 3-byte error into a 4-byte error which is now beyond the ability of the error correcting function of the controller. Consequently, the system becomes incapable of correcting even 3-byte errors.
Nevertheless, leaving the error correcting function of the flash memory chip unused is problematic in that the system has a needlessly large circuit area and is needlessly expensive due to the unused function.
If it is attempted to design a system having a more reliable error correcting function by use of a flash memory chip with an error correcting function as core element, it will be necessary to take a design procedure as shown by the flowchart of FIG.
18
A and the block diagram of flash memory chip of
FIG. 18B
, in which step
1501
removes the error correcting function block
1512
of the flash memory chip
1511
, step
1502
redesigns the interface block for the flash memory chip
1511
to make a new flash memory
1513
, and step
1503
designs a controller
1514
and an error correcting function block is included in the controller, and in consequence it will be problematic in an increased design work and a rising cost.
Devices of “memory stick” and MMC (Multi-Media Card) have their flash memory chip
1513
and controller
1514
integrated in one chip in order to reduce the size and weight. However, designing these devices also necessitates the procedure shown in
FIG. 18A
, resulting in an increased design work and rising cost.
Devices of a portable terminal and MPEG camera using a flash memory card (memory card formed of flash memory chips) often adopt a 512-byte unit data size of processing. Whereas, the flash memory chip has a trend of larger unit data sizes of erasure, e.g., 1024 bytes and 2048 bytes, with the intention of reducing circuit scale and speeding up per-byte processing speed. In this case, the error correction code is processed in the large unit data size of erasure.
Accordingly, it is necessary to read out data of 1024 bytes or more which is the unit data size of erasure to check the error correction code at each readout of data of 512 bytes which is the unit data size of processing, and also to read out data of 1024 bytes or more to re-calculate the error correction code at each writing of 512-byte data, resulting in an intricate process.
A high-reliability error correcting function involves high-speed computation, which needs a high-performance controller, and therefore it is expensive. However, flash memory cards used for the portable recording/reproduction device, etc. are required to be inexpensive more than being reliable.
SUMMARY OF THE INVENTION
The present invention is intended to overcome the foregoing prior art deficiencies and facilitate the design of a one chip semiconductor memory system which uses a memory chip core element with its error correcting function being kept active.
An object of the present invention is to provide a recording/reproduction device which uses a semiconductor memory with an error correcting function as core element, and which utilizes the error correcting function of the semiconductor memory and yet is more reliable in error correction than the semiconductor memory, and provide a semiconductor memory and which are useful for the recording/reproduction device.
Another object of the present invention is to provide a semiconductor memory and a memory chip which can simplify the process even in the case of having a unit data size of erasure larger than the unit data size of processing of devices which use these parts.
Still another object of the present invention is to provide a recording/reproduction device which is fairly reliable and is inexpensive.
At a first viewpoint, the present invention resides in a recording/reproduction device comprising a controller section having a first error correction code generator which generates a first error correction code for data put in from the outside, and a first error corrector which implements the error detection and correction by using the first error correction code, and a semiconductor memory section having a second error correction code generator which generates a second error correction code for the first error correction code provided by the controller section, a memory which stores the data from the controller section, a first error correction code check symbol which is the first error correction code, with the data being excluded therefrom, and a second error correction code check symbol which is the second error correction code, with the data and first error correction code check symbol being excluded therefrom, and a second error corrector which implements the error detection and correction by using the data and first and second error correction code check symbols read out of the memory, the second error correction code being a BCH code in the same Galois field as the first error correction code and having a continuous root, the controller section implementing the error correction by using the error correction result provided by the second error correc
Katayama Yukari
Nakamura Kazuo
Antonelli Terry Stout & Kraus LLP
Chase Shelly A
Hitachi , Ltd.
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