Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Patent
1995-12-27
1998-07-28
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
711157, 36518902, 36518904, 36525002, 36523003, 36523005, G06F 1202, G06F 1316, G11C 800
Patent
active
057874549
ABSTRACT:
A buffer comprises a memory array, a write circuit and a read circuit. The memory array comprises one or more memory banks. Each of the memory banks is made up of a plurality of memory cells. Each memory cell has one read port and one write port. The write circuit stores a first variable number of data items to the one or more memory banks by utilizing the one write port of a portion of the memory cells. The read circuit reads a second variable number of data outputs from the one or more memory banks by utilizing the one read port of a portion of the memory cells. At least of portion of the plurality of memory cells may include one or more additional write ports which are not used for writing the first variable number of data inputs to the one or more memory banks, and at least of portion of the plurality of memory cells may include one or more additional read ports which are not used for reading the second variable number of data outputs from the one or more memory banks. Additionally, the memory array comprises one or more write bitlines that share discontinuous metal tracks with one or more read bitlines.
REFERENCES:
patent: 5371877 (1994-12-01), Drako et al.
patent: 5434818 (1995-07-01), Byers et al.
patent: 5442747 (1995-08-01), Chan et al.
patent: 5544351 (1996-08-01), Lee et al.
Bragdon Reginald G.
Chan Eddie P.
Intel Corporation
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