Recorder buffer capable of detecting dependencies between access

Details Recorder buffer capable of detecting dependencies between access Recorder buffer capable of detecting dependencies between access

1995-11-20

1998-06-09

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711119, 711128, 711144, G06F 930, G06F 1200

Patent

active

057650357

ABSTRACT:
A dependency checking structure is provided which compares memory accesses performed from the execution stage of the instruction processing pipeline to memory accesses performed from the decode stage. The decode stage performs memory accesses to a stack cache, while the execution stage performs its accesses (address for which are formed via indirect addressing) to the stack cache and to a data cache. If a read memory access performed by the execution stage is dependent upon a write memory access performed by the decode stage, the read memory access is stalled until the write memory access completes. If a read memory access performed by the decode stage is dependent upon a write memory access performed by the execution stage, then the instruction associated with the read memory access and subsequent instructions are flushed. Data coherency is maintained between the pair of caches while allowing stack-relative accesses to be performed from the decode stage. The comparator circuits used to perform the comparison are configured to compare a field of address bits instead of the entire address, reducing the size while still maintaining accurate dependency checking by qualifying the resulting comparison signals with an indication that both addresses hit in the same storage location within the stack cache.

REFERENCES:
patent: 4044338 (1977-08-01), Wolf
patent: 4453212 (1984-06-01), Gaither et al.
patent: 4807115 (1989-02-01), Torng
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5226130 (1993-07-01), Favor et al.
patent: 5251306 (1993-10-01), Tran
patent: 5345569 (1994-09-01), Tran
patent: 5404470 (1995-04-01), Miyake
patent: 5416913 (1995-05-01), Grochowski et al.
patent: 5434987 (1995-07-01), Abramson et al.
patent: 5467473 (1995-11-01), Kahle et al.
patent: 5471598 (1995-11-01), Quattromani et al.
patent: 5487156 (1996-01-01), Popescu et al.
patent: 5497499 (1996-03-01), Grag et al.
patent: 5522052 (1996-05-01), Inoue et al.
patent: 5560032 (1996-09-01), Nguyen et al.
patent: 5590352 (1996-12-01), Zuraski, Jr. et al.
Intel, "Chapter 2: Microprocessor Architecture Overview," pp. 2-1 through 2-4.
Michael Slater, "AMD's K5 Designed to Outrun Pentium, " Microprocessor Report, vol. 8, No. 14, Oct. 24, 1994, 7 pages.
Sebastian Rupley and John Clyman, "P6: The Next Step?, " PC Magazine, Sep. 12, 1995, 16 pages.
Tom R. Halfhill, "AMD K6 Takes On Intel P6, " BYTE, Jan. 1996, 4 pages.
V. Popescu et al. "The Metaflow Architecture", IEEE Micro, pp. 10-13, 63-73, Jun. 1991.

Affiliated with

Also associated with

Rating

Recorder buffer capable of detecting dependencies between access does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Recorder buffer capable of detecting dependencies between access, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Recorder buffer capable of detecting dependencies between access will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2214773