Reconstruction of signal timing in integrated circuits

Details Reconstruction of signal timing in integrated circuits Reconstruction of signal timing in integrated circuits

2006-10-19

2009-02-10

Dinh, Son T (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S189080, C365S233100

Reexamination Certificate

active

07489569

ABSTRACT:
Improved integrated circuits, memory devices, circuitry, and data methods are described that facilitate the adjustment and reconstruction of signal timing of devices by providing for an interface having inputs and/or outputs that are adjustably delayed. This allows embodiments of the present invention to sense the signal delay and utilize adjustable input or output delays to correct the signal timing relationships such that correctly timed communication signals are received by the internal circuitry of the device. In one embodiment of the present invention, a register is utilized to adjust the timing delay of individual input and/or output signals for the device. This increases the robustness of the device and its resistance to communication or data corruption, allowing larger ranges of environmental conditions and input capacitances of systems or communication busses to be tolerated.

REFERENCES:
patent: 5655105 (1997-08-01), McLaury
patent: 5793688 (1998-08-01), McLaury
patent: 5867496 (1999-02-01), Peres et al.
patent: 6029250 (2000-02-01), Keeth
patent: 6101197 (2000-08-01), Keeth et al.
patent: 6111812 (2000-08-01), Gans et al.
patent: 6130856 (2000-10-01), McLaury
patent: 6269451 (2001-07-01), Mullarkey
patent: 6271682 (2001-08-01), Lindsay
patent: 6272070 (2001-08-01), Keeth et al.
patent: 6297998 (2001-10-01), Van de Graaff et al.
patent: 6304511 (2001-10-01), Gans et al.
patent: 6317381 (2001-11-01), Gans et al.
patent: 6327196 (2001-12-01), Mullarkey
patent: 6359815 (2002-03-01), Sato et al.
patent: 6378079 (2002-04-01), Mullarkey
patent: 6438043 (2002-08-01), Gans et al.
patent: 6445624 (2002-09-01), Janzen et al.
patent: 6445643 (2002-09-01), Keeth et al.
patent: 6499111 (2002-12-01), Mullarkey
patent: 6587804 (2003-07-01), Johnson et al.
patent: 6605969 (2003-08-01), Mikhalev et al.
patent: 6618829 (2003-09-01), Pax et al.
patent: 6643789 (2003-11-01), Mullarkey
patent: 6687185 (2004-02-01), Keeth et al.
patent: 6704881 (2004-03-01), Li et al.
patent: 6801989 (2004-10-01), Johnson et al.
patent: 6812760 (2004-11-01), Kim et al.
patent: 6813724 (2004-11-01), Saito
patent: 7069458 (2006-06-01), Sardi et al.
patent: 7106822 (2006-09-01), Guinea et al.
patent: 2001/0014048 (2001-08-01), Han
patent: 2001/0027507 (2001-10-01), Merritt
patent: 2001/0031027 (2001-10-01), Lindsay
patent: 2001/0044888 (2001-11-01), Li
patent: 2002/0135409 (2002-09-01), Gomm
patent: 2002/0154550 (2002-10-01), Ma et al.
patent: 19616857 (1996-10-01), None

Affiliated with

Also associated with

Rating

Reconstruction of signal timing in integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reconstruction of signal timing in integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reconstruction of signal timing in integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4100990