Reconfiguring storage modes in a memory

Details Reconfiguring storage modes in a memory Reconfiguring storage modes in a memory

2002-05-17

2003-12-02

Le, Thong Q. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S189040

Reexamination Certificate

active

06657881

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention pertains to the field of random access memories. More particularly, this invention relates to storage modes in a memory.
2. Art Background
A random access memory typically includes an array of storage cells. Each storage cell typically includes structures capable of changing storage states. For example, ferroelectric random access memories (FeRAMs) typically include ferroelectric capacitors capable of changing charge polarities. In another example, magnetic random access memories (MRAMs) commonly include magnetic films capable of changing magnetizations. The storage states of a storage cell usually indicate its logic state, i.e. a value of a bit that it stores.
Some memories implement a storage cell having a single storage structure capable of changing storage states. For example, a storage cell in a ferroelectric random access memory (FeRAM) may include a single ferroelectric capacitor capable of changing its charge polarity and a single transistor for accessing the stored state. Such a structure may be referred to as a one-transistor-one-capacitor (1T1C) cell structure. Similarly, an MRAM storage cell may be implemented with a single magnetic film structure capable of changing its magnetization.
A storage cell having a single storage structure is usually read by sensing its storage state and comparing the obtained signal to a reference. Typically, the reference is common for all the storage cells in a memory. If a signal sensed from a storage cell is greater than the reference then the storage cell is usually deemed to be in a first logic state and if the sensed signal is less than the reference then the storage cell is usually deemed to be in a second logic state.
The characteristics of the storage states in the storage cells of a memory typically vary due to variation in a manufacturing process as well as material fatigue over time and other factors. A relatively high variation in storage state characteristics usually increases the difficulty in selecting a reference which is suitable for reading all of the storage cells in a memory. If the variation among storage cells in a memory is large enough then a suitable reference may not be obtainable. Unfortunately, in such cases and the memory is usually discarded. Such discarding of individual memories usually decreases the yield of a manufacturing process and increases overall manufacturing costs.
Other memories implement a storage cell having dual storage structures each capable of changing storage states. For example, a storage cell in an FeRAM may include a pair of ferroelectric capacitors each capable of changing its charge polarity and a pair of corresponding transistors for accessing the stored states. Such a structure may be referred to as a two-transistor-two-capacitor (2T2C) cell structure. Similarly, an MRAM storage cell may be implemented with dual magnetic film structures each capable of changing its magnetization.
A storage cell having dual storage structures is usually read by sensing both its storage states and performing a differential comparison on the sensed signals. Such memories are usually less susceptible to the problems caused by manufacturing variation and material fatigue etc., because such variation tend to influence the storage structures in a complementary fashion. Such storage cells however, limit the amount of data storage density in a memory due to the additional storage structures.
SUMMARY OF THE INVENTION
A memory is disclosed which is capable of reconfiguration between a first mode in which each storage cell is capable of storing a pair of data bits and a second mode in which each storage cell is capable of storing a single data. A memory according to the present teachings includes a storage cell having a first structure and a second structure each capable of a storage state and mechanisms for reconfiguring the memory between a first mode in which the storage states of the first and second structures indicate a first and a second data bit, respectively, and a second mode in which the storage states combine to indicate a data bit. The present techniques enable reconfiguration of the memory at the time of manufacture or at a later time in response to measured characteristics of the storage cells.
Other features and advantages of the present invention will be apparent from the detailed description that follows.


REFERENCES:
patent: 6038162 (2000-03-01), Takata et al.
patent: 6249841 (2001-06-01), Sikes et al.
patent: 6310797 (2001-10-01), Muneno
patent: 6496428 (2002-12-01), Ohno et al.

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