Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-08-30
2005-08-30
Nguyen, T (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S142000, C711S143000, C711S144000, C711S154000, C711S155000, C711S170000, C711S171000
Reexamination Certificate
active
06938127
ABSTRACT:
A processor-based system includes a system firmware program that is transferred to a designated region of a memory in response to an initialization (e.g., a boot sequence). When initialized, for example using at least one programmable register, the system firmware program reconfigures the memory from a first configuration (i.e., a default state) to a second configuration to receive a pattern. By changing the memory to the second configuration, the memory may be declared to be a write combining type. For storage into the memory, the pattern may be buffered in one or more data blocks. Once the pattern is stored, the memory may be restored to the first configuration. Buffered data transfers of the pattern may selectively clear the memory thus providing a rapid booting of the processor-based system.
REFERENCES:
patent: 6223258 (2001-04-01), Palanca et al.
patent: 6334171 (2001-12-01), Hill et al.
patent: 6411302 (2002-06-01), Chiraz
patent: 6581148 (2003-06-01), Sadashivaiah et al.
patent: 6678807 (2004-01-01), Thatcher et al.
Fletcher Terry M.
Stevens William A.
Nguyen T
Stutman-Horn Ioni D.
LandOfFree
Reconfiguring memory to reduce boot time does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Reconfiguring memory to reduce boot time, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reconfiguring memory to reduce boot time will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3455034