Reconfigured wafer alignment

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S124000, C438S127000, C257SE23116

Reexamination Certificate

active

07943423

ABSTRACT:
A method of manufacturing semiconductor device comprises placing multiple chips onto a carrier. An encapsulation material is applied to the multiple chips and the carrier for forming an encapsulation workpiece. The encapsulation workpiece having a first main face facing the carrier and a second main face opposite to the first main face. Further, marking elements are applied to the encapsulation workpiece relative to the multiple chips, the marking elements being detectable on the first main face and on the second main face.

REFERENCES:
patent: 6326240 (2001-12-01), Liaw
patent: 6602734 (2003-08-01), Wada et al.
patent: 2006/0065964 (2006-03-01), Ohsumi
patent: 2006/0094161 (2006-05-01), Tao

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Reconfigured wafer alignment does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reconfigured wafer alignment, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reconfigured wafer alignment will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2646368

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.