Reconfiguration of a programmable logic device using...

Details Reconfiguration of a programmable logic device using... Reconfiguration of a programmable logic device using...

2007-06-05

2007-06-05

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S039000, C326S041000

Reexamination Certificate

active

11100971

ABSTRACT:
A method of partially reconfiguring an IC having programmable modules that includes the steps of reading a frame of configuration information from the configuration memory array; modifying at least part of the configuration information, thereby creating a modified frame of configuration information; and overwriting the existing frame of configuration information in the configuration memory array with the modified frame, thereby partially reconfiguring the IC.

REFERENCES:
patent: 6078735 (2000-06-01), Baxter
patent: 6096091 (2000-08-01), Hartmann
patent: 6128770 (2000-10-01), Agrawal et al.
patent: 6204687 (2001-03-01), Hung et al.
patent: 6304101 (2001-10-01), Nishihara
patent: 6429682 (2002-08-01), Schultz et al.
patent: 6483342 (2002-11-01), Britton et al.
patent: 6493862 (2002-12-01), Young et al.
patent: 6526557 (2003-02-01), Young et al.
patent: 6629311 (2003-09-01), Turner et al.
patent: 6851047 (2005-02-01), Fox et al.
Nick Camilleri; XAPP153, Application Note, “Status and Control Semaphore Registers Using Partial Reconfiguration”; Jun. 7, 1999 (Version 1.0); available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 1-4.
Xilinx, Inc.; XAPP151, Application Note: Virtex Series, “Virtex Series Configuration Architecture User Guide”; Sep. 27, 2000 (V1.5); available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 1-45.
Xilinx, Inc.; XAPP138, Application Note: Virtex Series, “Virtex FPGA Series Configuration and Readback”; Nov. 5, 2001 (v2.5); available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 1-39.
Xilinx, Inc.; Virtex-II Pro Platform FPGA Documentation; “Rocket I/O Transceiver User Guide”; Mar. 2002 Release; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 1059-1150.
Xilinx, Inc.; Virtex-II Pro, Platform FPGA Handbook; Oct. 14, 2002 (v2.0); available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 1-589.
Xilinx, Inc.; Virtex-II Pro Platform FPGA Documentation; “Advance Product Specification”; Mar. 2002 Release; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 1-342.
Xilinx, Inc.; Virtex-II Pro Platform FPGA Documentation; “PPC 405 User Manual,”; Mar. 2002 Release; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 343-870.
Xilinx, Inc.; Virtex-II Pro Platform FPGA Documentation; “PPC 405 Processor Block Manual”; Mar. 2002 Release; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 871-1058.
Raphael David et al.; “DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints”; Parallel and Distributed Processing Symposium; Proceedings International, IPDPS 2002; Apr. 15-19, 2002; pp. 156-163.
Davin Lim and Mike Peattie; XAPP290; “Two Flows for Partial Reconfiguration: Module Based or Small Bit Manipulations”; V1.0, May 17, 2002; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 1-23.

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