Reconfigurable programmable logic device

Details Reconfigurable programmable logic device Reconfigurable programmable logic device

1996-08-19

1997-12-09

Hudspeth, David R.

Electronic digital logic circuitry

Multifunctional or programmable

Array

36518908, 326 44, H03K 19177

Patent

active

056964552

ABSTRACT:
The present invention provides a reconfigurable programmable logic device (PLD) that saves its own programmed state without the use of an external memory device or without additional control logic on the PLD. A non-volatile memory cell is incorporated with each SRAM cell in the PLD to form a configuration memory cell. The non-volatile memory cells store the programmed states of the associated SRAM cells even after termination of power to the system. Each non-volatile memory cell then restores the configured state of its associated SRAM cell upon system power-up by "mapping" its contents to the SRAM cell. The non-volatile memory cell may be implemented either by an Erasable Programmable Read Only Memory cell ("EPROM") or an Electrically Erasable Programmable Read Only Memory cell ("EEPROM").

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Lipp et al., "A High Density Flash Memory FPGA Family," IEEE 1996 Custom Integrated Circuits Conference, pp. 239-242, 1996.

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