Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2004-10-01
2008-12-30
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S100000, C711S118000, C711S154000
Reexamination Certificate
active
07472224
ABSTRACT:
In one embodiment, a processing node includes a first processor core and a second processor core. The first processor core includes a first cache memory, such as an L2 cache, for example. The second processor core includes a second cache memory, such as an L2 cache memory. The processing node further includes a configuration unit that is coupled to the first processor core and the second processor core. The configuration unit may selectably disable portions of the first and the second cache memories.
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Thai Tuan V.
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