Reconfigurable parallel look up table system

Details Reconfigurable parallel look up table system Reconfigurable parallel look up table system

2002-04-24

2004-12-07

Kim, Hong (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S216000, C711S217000, C711S219000, C711S220000, C711S221000, C711S170000

Reexamination Certificate

active

06829694

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a reconfigurable parallel look-up table system
BACKGROUND OF THE INVENTION
Present communication applications such as current second generation (2G) personal digital assistants (PDA's), as well as the new (3G) mobile wireless handsets/terminals, call for MPEG-4 streaming video protocol. The latest generation video compression/decompression standards primarily targeted at devices with medium-speed data communication links. Look-up tables are massively used in both technologies. For example, in communication, forwarded error correction (Reed-Solomon) usually uses a 256 Galois field look-up table, data encryption algorithms like (DES/3DES, AES) use eight 64 byte look-up tables for the selection boxes (S-Box). In video streaming, protocols such as JPEG, MPEG-2, MPEG-4 and Windows Media, uses Huffman look-up tables for variable length coding (VLC). Traditional DSP and controllers access these tables serially which result in slow response time.
Typically, once these tables are designed for a particular task they are not adaptable for other uses. As a result, serially accessible look-up tables limit the speed of operation of communication and image processing applications.
BRIEF SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide an improved reconfigurable parallel look-up table system.
It is a further object of this invention to provide such an improved reconfigurable parallel look-up table system which can access a number of look-up tables simultaneously.
It is a further object of this invention to provide such an improved reconfigurable parallel look-up table system which is easily reconfigurable to access different numbers and different sizes of look-up tables.
It is a further object of this invention to provide such an improved reconfigurable parallel look-up table system which is faster and more flexible.
The invention results from the realization that a truly faster and more flexible look-up table system can be achieved by enabling a number of look-up tables in a memory to be accessed simultaneously by combining the values to be looked up with the values representing the starting addresses of the look-up tables to simultaneously translate each value into an address to locate in parallel the function of those values in each look-up table.
This invention features a reconfigurable parallel look-up table system including a memory and a plurality of look-up tables stored on the memory. A row index register holds the values to be looked up in the look-up tables, and the column index register stores the value representing the starting address of each of the look-up tables stored in the memory. An address translation circuit is responsive to the column index register and the row index register to simultaneously generate an address for each value in the row index register to locate in parallel the functions of those values in each look-up table.
In a preferred embodiment, the address translation circuit may include a multiplier circuit for multiplying the value representing the starting address by the length of each column and an adder circuit for combining the value in the row index register with the output of the multiplier circuit. The address translation circuit may include an OR circuit for combining the values from the row index register with the values in the column index register shifted toward the MSB by N bits in respect to the values in the row index register. The look-up tables may be all the same size.


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