Reconfigurable multi-way associative cache memory

Details Reconfigurable multi-way associative cache memory Reconfigurable multi-way associative cache memory

1991-12-26

1994-11-22

Dixon, Joseph L.

Boots, shoes, and leggings

395425, 3642647, 36424341, 3649272, G11C 1300

Patent

active

053676530

ABSTRACT:
A reconfigurable set associative cache memory can be reconfigured from 2.sup.x way to 2.sup.y way set associative cache memory by effectively merging a predetermined number of least significant bits of the tag field of the main memory address with the line field of the main memory address. The effective merging is provided by logically merging least significant bits of the tag field with a reconfiguration designation. As a result, Y-X+1 different configurations of cache memory can be obtained using the Y-X least significant bits of the tag field merged with the cache memory address.

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Cache Reconfiguration, J. Hrustich et al., IBM Technical Disclosure Bulletin, vol. 23, No. 9, Feb. 1981.
Memory Organization, Computer System Architecture, M. M. Mano, Second Edition, Prentice-Hall, Inc., pp. 478-521.

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