Reconfigurable multi-chip modules

Details Reconfigurable multi-chip modules Reconfigurable multi-chip modules

2001-05-01

2004-08-17

Baderman, Scott (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

Reexamination Certificate

active

06779131

ABSTRACT:

BACKGROUND OF INVENTION
Generally, a microprocessor operates much faster than main memory can supply data to the microprocessor. Therefore, many computer systems temporarily store recently and frequently used data in smaller, but much faster cache memory. Cache memory may reside directly on the microprocessor chip (Level 1 cache) or may be external to the microprocessor (Level 2 cache). In the past, on-chip cache memory was relatively small, 8 or 16 kilobytes (KB); however, more recent microprocessor designs have on-chip cache memories of 256 and even 512 KB.
Referring to
FIG. 1
, a typical computer system includes a microprocessor (
10
) having, among other things, a CPU (
12
), a load/store unit (
14
), and an on-board cache memory (
16
). The microprocessor (
10
) is connected to a main memory (
18
) that holds data and program instructions to be executed by the microprocessor (
10
). Internally, the execution of program instructions is carried out by the CPU (
12
). Data needed by the CPU (
12
) to carry out an instruction are fetched by the load/store unit
14
. Upon command from the CPU (
12
), the load/store unit (
14
) searches for the data first in the cache memory (
16
), then in the main memory (
18
).
As will be readily apparent to those skilled in the art, as the size of on-chip cache memory increases, the amount of data kept closely to the microprocessor for faster processing increases. Unfortunately, it is also a reality in microprocessor manufacturing that as on-chip cache memory size increases, the potential for producing memory with faulty regions increases. Techniques have been used in the industry to attempt to combat the loss of manufacturing yield due to these unusable sections of memory. For example, if the faulty memory region lies with one or more columns of the memory array, other columns may be mapped to “cover” the unusable columns.
Typically, a Multi-Chip Module (MCM) includes one or more processors and one or more SRAMS. Testing of the MCM is done at various stages of the manufacturing process. There are yield issues at various levels in an MCM. Dies are tested at the wafer level and, if found good, are assembled on the MCM. Testing at wafer level is well known in the art and has been used for many years now. Alternatively, dies for an MCM could come from different fabs, i.e., manufacturing plants that make semiconductor devices. Limited testing of the dies does occur at the fabs. Testing is done after all the dies are assembled and packaged.
One well known way of testing Static Random Access Devices (SRAM) in an MCM module is the RAMTEST function. The RAMTEST function works by selecting a SRAM connected to the processor, writing a bit pattern to a specific address in the selected SRAM, and reading from the specific address in the selected SRAM. Upon reading the data from the specific address in the selected SRAM, faulty rows and columns in the SRAM can be identified. One well known algorithm for performing the RAMTEST function is included below.
I
For (addr=0; addr < N; addr++) // Ascending order
Write (v); // memory initialization
II
For (addr=0; addr < N; addr++)
{
Read(v);
Write(vbar);
Read(vbar);
} // vbar is negate of v
III
For (addr=N.1; addr>=0; addr..) // Descending order
{
Write(v);
Read(v);
}
Notes: Checker board data pattern can be used
The SRAM faults detected by the above algorithm are stored in a special RAMTEST fault register (FREG), which has 8 bits. Those skilled in the art will appreciate that the dies may go through a limited testing at wafer sort, i.e., prior to assembly.
SUMMARY OF INVENTION
In general, in one aspect, the present invention involves a reconfigurable multi-chip module comprising a processor; a memory module connected to the processor; and a memory control component for controlling whether the processor uses the memory module.
In general, in one aspect, the present invention involves a method of producing multi-chip modules comprising assembling a processor and a memory module on the multi-chip module; testing the memory module; and selectively configuring the processor to use the memory module based on the testing of the memory module.
In general, in one aspect, the present invention involves a reconfigurable multi-chip module comprising processing means; memory means connected to the processing means; and control means for determining whether the processing means uses the memory means.
In general, in one aspect, the present invention involves a reconfigurable multi-chip module comprising a processor comprising a memory control component; a first memory module connected to the processor; and a second memory module connected to the processor, wherein the memory control component determines whether the processor uses the first memory module and the second memory module.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.


REFERENCES:
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patent: 6060339 (2000-05-01), Akram et al.
patent: 6081463 (2000-06-01), Shaffer et al.
patent: 6154851 (2000-11-01), Sher et al.
patent: 6204562 (2001-03-01), Ho et al.
patent: 6363502 (2002-03-01), Jeddeloh
patent: 6405324 (2002-06-01), Shore
patent: 6483755 (2002-11-01), Leung et al.
patent: 6530005 (2003-03-01), Koschella et al.

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