Reconfigurable memory circuit

Details Reconfigurable memory circuit Reconfigurable memory circuit

1978-10-25

1981-03-03

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Bad bit

307238, 365190, 365207, G11C 1140, G11C 1300

Patent

active

042544777

ABSTRACT:
The disclosed device uses an interconnect switch for the selective coupling of serial memory elements in series with other memory elements. A control unit may test elements, designate some of the elements as operable for use and designate other elements as spares. The memory system is defined by the states of interconnection which couple the memory elements either for operation or for sparing, and which uncouple the defective memory element from use in the system. Upon the failure of an element which is being used the control unit can switch out the defective memory cell and switch in a replacement element or simply bypass the defective element. This technique is particularly useful for wafer scale integration where a plurality of functional elements are contained on a single wafer; particularly in memory arrays which are individually addressable. However, this technique also allows the selective replacing of elements within the particular array to ensure the proper number of memory cells within the array. Individual selection of such memory cells allows the insertion of random sparing elements such that any memory cell within the string that becomes defective may be switched out and a new cell added at any point in the string thereby preventing the necessity of dual or triple redundancy for each cell. This switching ability or the adaptive feature of the circuit makes it possible to implement sparing to produce high reliability electronic systems while utilizing a minimum number of spare microcircuits on the wafer, or in a wired system composed of discrete LSI parts.

REFERENCES:
patent: 3346847 (1967-10-01), Faulkner
patent: 4007452 (1977-02-01), Hoff et al.
patent: 4133049 (1979-01-01), Shirato

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