Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2008-07-11
2010-12-28
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S097000, C326S098000, C326S104000, C326S114000, C326S121000
Reexamination Certificate
active
07859308
ABSTRACT:
Reconfigurable logic cells based on dual gate MOSFET transistors (DG MOSFETs) including n inputs (A,B), n being greater than or equal to 2 and capable of performing at least four logic functions with which logical signals provided on the n inputs (A,B) may be processed. The cell contains, between the ground and the output (F) of the cell, at least one first branch including n dual gate N-type MOSFET transistors (M1,M2) in series and n−1 branches in parallel with the first branch, each provided with a dual gate N-type MOSFET transistor (M3), each of the logic functions corresponding to a given configuration of the cell. A specific set of control signals (C1,C2) is applied on the rear gates of at least one portion of the transistors (M2,M3), each control signal (C1,C2) being capable of setting the transistor (M2,M3) to a particular operating mode.
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Hassoune Ilham
O'Connor Ian D.
Centre National de la Recherche Scientifique "CNRS"
Cho James H.
Crawford Jason M
Dennison, Schultz & Macdonald
Ecole Centrale de Lyon
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