Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-10-10
2009-11-10
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07617470
ABSTRACT:
Methods are disclosed to increase yielded performance of a reconfigurable integrated circuit; improve performance of an application running on a reconfigurable integrated circuit; reduce degradation of an integrated circuit over time; and maintain performance of an integrated circuit time.
REFERENCES:
patent: 5475605 (1995-12-01), Lin
patent: 6340901 (2002-01-01), Molnar
patent: 7373538 (2008-05-01), Eldin et al.
patent: 2004/0060032 (2004-03-01), McCubbrey
Alfred K. Yeung et al. “A 2.4-GOPS Data-Drivern Reconfigurable Multiprocessor IC for DSP,” Proceeding of the 1995 IEE International Solis-State Circuits Conference, pp. 108-109.
Seth C. Goldstein et al. “PipeRench; A Coprocessor for Streaming Multimedia Acceleration” ISCA, pp. 28-39, May 1999.
Helia Naeimi et al. “A Greedy Algorithm for Tolerating Defective Crosspoints in Nano PLA Design”, IEEE International Conference on Field-Programmable Technology, Dec. 6-8, 2004, pp. 1-9.
Vaughn Betz et al. “VPR: A New Packing Placement and Routing Tool for FPGA Research”, 1997 Internatinal Workshop on Field Programmable Logic and Applications,pp. 1-10.
Dmitri B. Strukov et al. “A Reconfigurable Architecture for Hybrid CMOS/Nanodevice Circuits”, FPGA3 06, Feb. 22-24, 2006.
Dmitri B. Strukov et al. CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices, Nanotechnology vol. 16, Apr. 19, 2005, pp. 888-900.
Dev C. Chen et al. “A Reconfigurable Multiprocessor IC for Rapid Prototyping of Algorithmic-Specific High-Speed DSP Data Paths”,IEEE Journal of Solid-state circuits, vol. 27, No. 12 Dec. 1992, pp. 1895-1904.
Greg Snider et al. “CMOS-like logic in defective, nanoscale crossbars”, Nanotechnology vol. 15, Jun. 9, 2004, pp. 881-891.
Mattia Ruffoni et al. “Direct Measures of Path Delays on Commercial FPGA Chips”, Signal Propagation on Interconnects, 6thIEEE Workshop on. Proceedings, May 12-15, 2002, pp. 157-159.
John Emmert et al. “Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration”, 2000, pp. 165-174.
Xiao-Yu Li et al. “FPGA as Process Monitor-An Effective Method to Characterize Poly Gate C Variation and its Impact on Product Performance and Yield”, IEEE Transactions on Semiconductor Manufacturing, vol. 17, No. 3, Aug. 2004, pp. 267-272.
Todd Austin et al., “Making Typical Silicon Matter with Razor”, IEEE Computer Society, Mar. 2004, pp. 57-65.
Ethan Mirsky et al. “MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources”, FCCM'96-IEEE Symposium on FPGA's for Custom Computing Machines, Apr. 17-19, 1996, Pages.
Seth Copen Goldstein et al. “NanoFabrics: Spatial Computing Using Molecular Electronics”, Proc. Of the 28thAnnual International Symposium on Computer Architecture, Jun. 2001, pp. 1-12.
Victor A. Sverdlov et al. “Nanoscale silicon MOSFETs : A Theoretical Study”, IEEE Transactions on electron devices, vol. 50, No. 9, Sep. 9, 2003.
Andre Dehin, “Nanowire Based Programmable Architectures”, ACM Journal on Emerging Technologies in Computing Systems, vol. 1, No. 2, Jul. 2005, pp. 109-162.
Charles Stroud et al. “On-Line BIST and Diagnosis of FPGA Interconnect Using Roving STARs”, On-Line Testing Workshop, 2001. Proceedings. Seventh International, 2001, pp. 27-33.
Larry McMurchie et al. “Pathfinder: A Negotiation-Based Performance-Driven Router for FPGAs”, Proceedings of the third ACM Symposium on Field-Programmable Gate Arrays , Monterey, Feb. 1995, pp. 111-117.
S. Kirkpatrick et al., “Optimization by Simulated Annealing”, vol. 220, No. 4598, May 13, 1983, pp. 671 to 680.
Carl Ebeling at al. “RaPID-Reconfigurable Pipelined Datapath”, pp. 126-135.
Andre Dehon et al. “Seven Strategies for Tolerating Highly Defective Fabrication”, Advanced Technologies and Reliable Design for Nanotechnology System, Jul.-Aug. 2005, pp. 306-315.
Andre Dehon et al. “Stream computations organized for reconfigurable execution”, Microprocessor and Microsystems 30, Mar. 2006, pp. 334-354.
Yi Luo et al. “Two-Dimensiona Molecular Electronics Circuits”, Chemphyschem, 2002, pp. 519-525.
Subhasish Mitra et al., “Which Concurrent Error Detecting Scheme to Choose”, Proceedings of the 2000 IEEE International Test Conference, 2000, p. 985.
Kazuya Katsuki et al. “A Yield and Speed Enhancement Scheme under Within-die Variations on 90nm LUT Array”, IEEE 2005 Custom Integrated Circuits Conference, 2005, pp. 601-604.
Xiao-Yu Li et al., “FPGA as Process Monitor An Effective Method to Characterize Poly Gate CD Variation and its Impact on Product Performance and Yield”, IEEE Transactions on Semiconductor Manufacturing, vol. 17, No. 3, Aug. 2004, pp. 267-272.
PCT International Search Report for PCT/US2006/039779 in the name of California Institute of Technology filed on Oct. 10, 2006.
International Preliminary Report on Patentability, PCT/US2006/039779 in the name of California Institute of Technology filed on Oct. 10, 2006.
Dehon Andre M.
Gojman Benjamin
California Institute of Technology
Siek Vuthe
Steinfl & Bruno
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