Reconfigurable I/O DRAM

Details Reconfigurable I/O DRAM Reconfigurable I/O DRAM

1997-04-04

2000-05-30

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

G11C 2900

Patent

active

060702621

ABSTRACT:
A Dynamic Random Access Memory (DRAM) configurable by eight (.times.8) or by nine (.times.9). The DRAM has nine Data Input/Outputs (I/Os). The memory array is divided into two or more sub-arrays, with sub-array cells arranged in addressable rows and columns. When the DRAM is configured .times.8, one I/O is held in its high impedance state; one ninth of the DRAM's data path (between the array and the ninth I/O) is ignored; and, the entire array address space is available for data storage through eight I/Os. When the DRAM is configured .times.9, all nine I/Os are active; the DRAM I/O path is reconfigured with part of the array providing the ninth bit through the ninth I/O; and the array address space reduced by one-eighth. All nine bits may be from a common sub-array. Alternatively, sub-arrays may be paired so that when the DRAM is configured .times.9, eight bits are accessed in seven-eighths of one sub-array, with the ninth bit being accessed in one eighth of the other sub-array of the pair.

REFERENCES:
patent: 4527251 (1985-07-01), Nibby, Jr. et al.
patent: 4612640 (1986-09-01), Mehrotra et al.
patent: 4651321 (1987-03-01), Woffinden et al.
patent: 4706249 (1987-11-01), Nakagawa et al.
patent: 5014187 (1991-05-01), Debize et al.
patent: 5109521 (1992-04-01), Culley
patent: 5228046 (1993-07-01), Blake et al.
patent: 5261064 (1993-11-01), Wyland
patent: 5278964 (1994-01-01), Mathews et al.
patent: 5289477 (1994-02-01), Lenta et al.
patent: 5293593 (1994-03-01), Hodge et al.
patent: 5313624 (1994-05-01), Harriman et al.
patent: 5386540 (1995-01-01), Young et al.
patent: 5404336 (1995-04-01), Imai
patent: 5537573 (1996-07-01), Ware et al.
patent: 5553023 (1996-09-01), Lau et al.
Patterson and Hennessy, Computer Organization & Design: The Hardware/Software Interface, pp. 475-476, 1994.

Affiliated with

Also associated with

Rating

Reconfigurable I/O DRAM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reconfigurable I/O DRAM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reconfigurable I/O DRAM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1919239