Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-06-06
2006-06-06
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07058918
ABSTRACT:
An exceptionally effective SoC design is achieved by the user of wrappers that comprise a functionally reconfigurable module (FRM) that is capable of affecting the operational functionality of the wrapper and that, consequently, is capable of affecting the operational functionality of a designed SoC. One embodiment of a core+wrapper combination comprises distinct input and output cells within the wrapper, and a separate FRM. Another embodiment may embed the input and output cells within the FRM. The FRM may be implemented with, for example, a field programmable logic array (FPLA). An additional advance is realized by providing a number of spare leads in the signal paths network that interconnects the various SoC elements.
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Koranne, Sandeep, “A Novel Reconfigurable Wrapper for Testing of Embedded Core-Based SOCs and its Associated Scheduling Algorithm”, Journal of Elctronic Testing: Theory and Applications, vol. 18, No. 4-5, Sep. 2002.
Huang, J.-R., et al., “A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs”; IEEE, pp. 198-203, 2001.
U.S. Appl. No. 10/379,043, filed Mar. 4, 2003.
Abramovici Miron
Dunlop Alfred E.
DAFCA, Inc.
Do Thuan
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