Reconfigurable device having programmable interconnect...

Details Reconfigurable device having programmable interconnect... Reconfigurable device having programmable interconnect...

2001-06-14

2002-10-22

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000

Reexamination Certificate

active

06469540

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to reconfigurable devices capable of implementing various functions programmably, and in particular, to programmable interconnect networks as major part of the reconfigurable devices.
DESCRIPTION OF THE RELATED ART
Reconfigurable devices such as PLD (Programmable Logic Device), FPGA (Field Programmable Gate Array), etc. which are capable of implementing various functions programmably are progressing remarkably in recent years. Such reconfigurable devices have been used for emulation in the designing of ASICs (Application Specific Integrated Circuits), as replacements for simple peripheral circuits, etc. However, by the technological innovation of these days, the reconfigurable device is now being expected to realize a “reconfigurable computers”, whose hardware architecture can be reconfigured to be adapted for each application.
In general, the reconfigurable device is composed of a two-dimensional array of function cells (to each of which various logical functions can be set programmably) and a programmable interconnect network which programmably connects the function cells and the other various circuits on the device (for example, I/O circuits, memory, etc.).
For the purpose of efficient interconnection between the function cells and the other various circuits on the device, a variety of programmable interconnect networks having hierarchical structure including lines of various lengths have been devised.
[Prior Art #1]
FIG. 1
is a circuit diagram showing an example of a conventional programmable interconnect network having such a hierarchical structure (hereafter, referred to as “prior art #1”)
FIG. 1
shows part (a row) of a two-dimensional function cell array and part of the programmable interconnect network corresponding to the row. The programmable interconnect network of the prior art #1 includes a plurality of programmable interconnect ways
20
corresponding to the rows of the two-dimensional function cell array, however, only one programmable interconnect way
20
is shown in FIG.
1
. The programmable interconnect way
20
shown in
FIG. 1
includes a short programmable interconnect channel
21
which is composed of short lines and a long programmable interconnect channel
22
which is composed of long lines. The short programmable interconnect channel
21
is segmented by programmable switches
58
-
1
and
58
-
2
into short sectors
65
-
1
, and the long programmable interconnect channel
22
is segmented by the programmable switches
58
-
2
into long sectors
65
-
2
.
Each programmable switch (
58
-
1
,
58
-
2
) is a circuit for programmably connecting/disconnecting the connection between lines which are connected thereto. Such a programmable switch (
58
-
1
,
58
-
2
) is capable of programmably connecting/disconnecting axially aligned and adjacent lines (such as the lines
62
-
1
and
62
-
2
) or lines running in different channels (such as the lines
61
-
1
and
62
-
1
).
In such interconnect line structure which is segmented into sectors (short sectors
65
-
1
, long sectors
65
-
2
), a signal to be transferred across multiple sectors has to pass through a lot of programmable switches (
58
-
1
,
58
-
2
). Such signal transfer across multiple sectors tends to introduce large delay in comparison with signal transfer in a sector. Further, such signal transfer delay is enhanced if the sizes of macro blocks which are implemented on the chip do not match the sector structure.
Especially when a circuit such as a “data path” (in which signals are successively transferred across nearby macro blocks and thereby a massive amount of conplicated data processing is performed consequently) is implemented on a sector type interconnect line structure such as the one shown in
FIG. 1
, some inter-macro-block connections are necessitated to pass through sector boundaries and thereby the aforementioned delay is caused.
Further, when a large-scale circuit is implemented on such a sector type interconnect line structure, a signal has to pass through many sector boundaries whether it is in a macro block or across macro blocks. For such reasons, high performance can not be attained in the sector type interconnect line structure.
Incidentally, the prior art #1 of
FIG. 1
is only a simple example for clearly showing the essence of the problems of conventional programmable interconnect networks. Therefore, the number of lines, the sizes of sectors, the number of programmable interconnect channels, etc. shown in
FIG. 1
are not essential. A typical programmable interconnect network corresponding to the prior art #1 has been disclosed in U.S. Pat. No. 5,469,003.
[Prior Art #2]
Another sector type interconnect line structure has been disclosed in U.S. Pat. No. 5,218,240 (hereafter, referred to as “prior art #2”). In the prior art #2, the short sectors
65
-
1
and the long sectors
65
-
2
which have been shown in
FIG. 1
are configured as common sectors. However, the function cells
10
in the prior art #2 are not connected to the long programmable interconnect channels
22
(referred to as “express buses” in the prior art #2) and are connected to the short programmable interconnect channels
21
(referred to as “local buses” in the prior art #2) only.
Therefore, the long programmable interconnect channel
22
in the prior art #2 is designed to make access to a function cell
10
through a programmable switch
58
-
2
and a short programmable interconnect channel
21
. By such composition, the load capacitance of the long programmable interconnect channel
22
is reduced and thereby high-speed signal transfer is realized.
However, in the interconnect line structure of the prior art #2, the interconnect network is totally segmented into sectors, without additional long interconnect line resources. Therefore, the demerits of the sector segmentation can not be compensated for at all, differently from the prior art #1 of
FIG. 1
in which the demerits could be partially compensated for by use of the long sector
65
-
2
which bypasses the boundaries of short sectors
65
-
1
.
[Prior Art #3]
Next, problems concerning the connection between the programmable interconnect network and the function cells
10
will be explained.
FIG. 2
is a circuit diagram showing a conventional connection method (hereafter, referred to as “prior art #3”) for connecting a hierarchical programmable interconnect network (not limited to sector type network) and function cells
10
. Such a connection method has been disclosed in AT&T Field-Programmable Gate Arrays Data Book (April 1995). The programmable interconnect network of the prior art #3 includes a plurality of horizontal programmable interconnect ways
20
which extend in the horizontal direction and a plurality of vertical programmable interconnect ways
30
which extend in the vertical direction. Incidentally, a horizontal programmable interconnect way
20
and a vertical programmable interconnect way
30
corresponding to a function cell
10
are shown in
FIG. 2
for the sake of simplicity.
The horizontal programmable interconnect way
20
show in
FIG. 2
at least includes a short horizontal programmable interconnect channel
21
and a long horizontal programmable interconnect channel
22
, and the vertical programmable interconnect way
30
at least includes a short vertical programmable interconnect channel
31
and a long vertical programmable interconnect channel
32
.
At the intersection
59
of the horizontal programmable interconnect way
20
and the vertical programmable interconnect way
30
, an intersection programmable switch
55
is provided so as to programmably connect/disconnect the connections between the intersecting lines.
The function cell
10
shown in
FIG. 2
includes an input selection switch
11
, a function block
13
and an output selection switch
15
. The function block
13
is provided with two or more functions and a function is programmably selected from the

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