Reconfigurable device

Details Reconfigurable device Reconfigurable device

2006-01-03

2006-01-03

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000

Reexamination Certificate

active

06982570

ABSTRACT:
A reconfigurable device comprises tiles and an interconnect architecture. Each of the tiles comprises a circuit. The interconnect architecture couples to the circuit of each tile and comprises switches and registers. In operation some of the switches route a signal from a first tile to a second tile along the interconnect architecture and at least two of the registers consecutively latch the signal at a time interval of no more than a repeating time period. In one embodiment of the reconfigurable device, the repeating time period comprises a clock cycle period. In another embodiment of the reconfigurable device, the repeating time period comprises a multiple of the clock cycle period.

REFERENCES:
patent: 4670749 (1987-06-01), Freeman
patent: 5600264 (1997-02-01), Duong et al.
patent: 5631578 (1997-05-01), Clinton et al.
patent: 5651013 (1997-07-01), Iadanza
patent: 6204690 (2001-03-01), Young et al.
patent: 6243851 (2001-06-01), Hwang et al.
patent: 6292022 (2001-09-01), Young et al.
patent: 6353841 (2002-03-01), Marshall et al.
patent: 6553395 (2003-04-01), Marshall et al.
V. Kathail, et al., PICO (Program In, Chip Out) : Automatically Designing Custom Computers, IEEE Computer, Sep. 2002, 35(9), pp. 39-47.
S. C. Goldstein, et al., PipeRench: A Reconfigurable Architecture and Compiler, IEEE Computer, Apr. 2000, 33(4), pp. 70-77.
S. C. Goldstein, et al., PipeRench: A Coprocessor for Streaming Multimedia Acceleration, In Proceedings of the 26th Annual International Symposium on Computer Architecture, 1999, pp. 28-39.
V. Betz and J. Rose, Effect of the Prefabricated Routing Track Distribution on FPGA Area-Efficiency, IEEE Transactions on VLSI, Sep. 1998, 6(3), pp. 445-456.
Emre Özer, Sanjeev Banerjia, and Thomas M. Conte, Unified Assign and Schedule: A New Approach to Scheduling for Clustered Register File Microarchitectures, In Proceedings of the 31th Annual International Symposium on Microarchitecture (MICRO-31), Dallas, Texas, 1998, pp. 308-315.
M.C. Papaefthymiou, Understanding Retiming Through Maximum Average-Delay Cycles, Mathematical Systems Theory, 1994, 1(27), pp. 65-84.
J. Babb, R. Tessier, and A. Agarwal, Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators, In Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, Los Alamitos, CA 1993, pp. 142-151.
J.S. Rose and S. Brown, Flexibility of Interconnection Structures for Field-Programmable Gate Arrays, IEEE JSSC, Mar. 1991, 26(3), pp. 277-282.
S. Note, et al., Cathedral III: Architecture driven high-level synthesis for high throughput DSP applications, In Proceedings of the 28th ACM/IEEE Design Automation Conference, DAC 91, San Francisco, CA, 1991, pp. 597-602.
Constantine N. Anagnostopoulos, Paul P. K. Lee, Application-Specific Integrated Circuits, The Electronics Handbook, pp. 731-748, CRC Press, Boca Raton FL, 1996.
Bradley K. Fawcett, Software Development Tools for Field Programmable Gate Array Devices, The Electronics Handbook, pp. 784-793, CRC Press, Boca Raton FL, 1996.

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