Reconfigurable cache controller for nonuniform memory access...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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C711S128000

Reexamination Certificate

active

06961821

ABSTRACT:
A method and structure for replacing cache lines in a computer system having a set associative cache memory is disclosed. The method establishes ranking guidelines utilizing a writable cache replacement control array, wherein the guidelines can be dynamically changed by writing data to the cache replacement control array. The invention ranks states of different cache lines according to the ranking guidelines and replaces, upon a cache miss, a cache line having a highest rank of the rankings.

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