Reconfigurable bit-manipulation node

Details Reconfigurable bit-manipulation node Reconfigurable bit-manipulation node

2007-03-27

2007-03-27

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S755000, C714S779000, C714S786000, C714S794000, C714S795000, C714S796000, C375S262000, C375S341000

Reexamination Certificate

active

10683563

ABSTRACT:
A reconfigurable bit-manipulation node is disclosed. The node includes an execution unit configured to perform a number of bit-oriented functions and a control unit configured to control the execution unit to allow one of the bit-oriented functions to be performed. The execution unit includes a number of elements interconnected with one another to allow the bit-oriented functions to be performed. The elements include a programmable butterfly unit, a number of non-programmable butterfly units, a number of data path elements, a look-up table memory, and a reorder memory. The execution unit is capable of engaging in one of a number of operating modes to perform the bit-oriented functions. The operating modes include a programmable mode and a number of fixed operating modes including Viterbi decoding, turbo decoding and variable length encoding and decoding. The data path elements include a programmable shifter and a programmable combiner.

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Bannatyne, R. ‘Migrating from 8- to 16-bit processors,’ Transp. Syst. Group, Motorola Inc., USA; Northcon/98 Conference Proceedings ; Oct. 21-23, 1998; pp. 150-158.

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