Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-12-19
2006-12-19
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07152214
ABSTRACT:
A method and apparatus for recognizing a state machine in circuit design in a high-level IC description language. The present invention analyzes high-level IC description language code, such as VHDL and Verilog®, of an IC design and extracts description information corresponding to a state machine. The description information can be, for example, the high-level IC description language code corresponding to the state machine, a state diagram of the state machine, a state table for the state machine, or other representation of the state machine. In one embodiment, the present invention identifies a set of one or more processes as defined by VHDL “process” statements. By identifying one or more clocked processes, one or more transition processes, and one or more output processes, the present invention provides a state machine summary to describe the state machine identified in the high-level IC description language code.
REFERENCES:
patent: 5537580 (1996-07-01), Giomi et al.
patent: 5680332 (1997-10-01), Raimi et al.
patent: 5774370 (1998-06-01), Giomi
patent: 6182268 (2001-01-01), McElvain
patent: 6292765 (2001-09-01), Ho et al.
Wang et al., “Practical FSM Analysis for Verilog,” IEEE, Mar. 1998, pp. 1-7.
“IEEE Standard VHDL Language Reference Manual,” ANSI Std. 1076-1993, Published Jun. 6, 1994.
“IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language,” IEEE Standard 1364-1995, Published Oct. 14, 1996.
Hoskote et al., “Automated Verification of Temporal Properties Specified as State Machine in VHDL,” IEEE, pp. 100-105, 1995.
Kam et al., “Comparing Layouts with HDL Models: A Formal Verification Technique,” IEEE, Apr. 4, 1995.
Cheng et al., Compiling Verilog into Timed Finite State Machines, IEEE, pp. 32-39, 1995.
Wu et al., “A Synthesis Method for Mixed Synchronous/Asynchronous Behavior,” IEEE, pp. 277-281, 1994.
Dane Mark W. P.
Gilford Michael E. J.
Reynolds Michael J.
Tredinnick Jacob L.
Walker Gordon N.
Klarquist & Sparkman, LLP
Siek Vuthe
LandOfFree
Recognition of a state machine in high-level integrated... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Recognition of a state machine in high-level integrated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Recognition of a state machine in high-level integrated... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3712093